Patent
Merging single precision floating point operands
TLDR
In this article, a first merge instruction copies the first and second single precision operands from respective first-and second-rows of the re-order buffer into first/second portions of a fifth row of the Reorder buffer, and then concatenates the third and fourth single-precision operands to represent a second double precision operand.Abstract:
Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a re-order buffer, and third and fourth single precision operands are loaded into third and fourth respective rows of the re-order buffer. A first merge instruction copies the first and second single precision operands from respective first and second rows of the re-order buffer into first and second portions of a fifth row of the re-order buffer, thereby concatenating the first and second single precision operands to represent a first double precision operand. A second merge instruction copies the third and fourth single precision operands from respective third and fourth rows of the re-order buffer into first and second portions of a sixth row of the re-order buffer, thereby concatenating the third and fourth single precision operands to represent a second double precision operand. The first and second double precision operands stored in the fifth and sixth rows, respectively, of the re-order buffer are then provided directly to an associated FPU for execution.read more
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Patent
Processor for executing wide operand operations using a control register and a results register
Patent
Prefix Computer Instruction for Compatibly Extending Instruction Functionality
TL;DR: In this paper, a prefix instruction is executed and passes operands to a next instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operators provided by the prefix instruction to perform an operation.
Patent
Using register last use infomation to perform decode-time computer instruction optimization
TL;DR: In this paper, a last-use register has a value that is not to be accessed by later instructions, where the two computer machine instructions are replaced by a single optimized internal instruction for execution.
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Patent
Data processing system for single-precision and double-precision data
Koichi Hatta,Koichi Kuroiwa +1 more
TL;DR: In this article, a data processing system includes a single-precision operation unit, a double-precision operation unit and a data conversion unit, where the singleprecis operation unit performs a single precision operation upon a group of single precision data, and the doublepreci cation unit performs double precision operation on the other group of double precision data.
Patent
Multi-pipeline microprocessor with data precision mode indicator
TL;DR: In this article, the data dependency check logic is used to compare register designations without knowing whether they are single or double precision. But it does not consider whether a register designation is a double or single precision operation.
Patent
Method and apparatus for using double precision addressable registers for single precision data
TL;DR: In this article, the same data can be written back to where they can be accessed as single precision data, and groups of data in addressable single precision registers are written as pairs using the double precision register address in the register file.