J
J. Chang
Researcher at Intel
Publications - 16
Citations - 608
J. Chang is an academic researcher from Intel. The author has contributed to research in topics: CPU cache & Xeon. The author has an hindex of 10, co-authored 13 publications receiving 573 citations.
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Journal ArticleDOI
A 45 nm 8-Core Enterprise Xeon¯ Processor
Stefan Rusu,Simon M. Tam,Harry Muljono,J. Stinson,David J. Ayers,J. Chang,Raj Varada,Matt Ratta,Sailesh Kottapalli,Sujal Vora +9 more
TL;DR: This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process to improve manufacturing yields and enable multiple product flavors from the same silicon die.
Journal ArticleDOI
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache
Stefan Rusu,Simon M. Tam,Harry Muljono,David J. Ayers,J. Chang,B. Cherkauer,J. Stinson,John Benoit,Raj Varada,Justin Leung,Rahul Limaye,Sujal Vora +11 more
TL;DR: This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process that implements both sleep and shut-off leakage reduction modes and employs multiple voltage and clock domains to reduce power.
Journal ArticleDOI
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series
J. Chang,Ming Huang,Jonathan Shoemaker,John Benoit,Szu-Liang Chen,Wei Chen,Siufu Chiu,Raghuraman Ganesan,G. Leong,Venkata Lukka,Stefan Rusu,Durgesh Srivastava +11 more
TL;DR: The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 mum2 cell in a 65-nm 8-metal technology to minimize both leakage and dynamic power.
Proceedings ArticleDOI
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache
TL;DR: A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process and implements both sleep and shut-off leakage reduction modes.
Proceedings ArticleDOI
A 45nm 8-core enterprise Xeon ® processor
Stefan Rusu,Simon M. Tam,Harry Muljono,David J. Ayers,J. Chang,Raj Varada,Matt Ratta,Sujal Vora +7 more
TL;DR: In this article, a 2.3B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24MB shared L3 cache was implemented in a 45nm 9-metal process.