This paper reviews the fundamentals and latest progress of modeling, analysis, and design technologies for signal integrity and electromagnetic compatibility on PCB and package in the past decades. Most results in this field are based on the very rich and highly educational literature produced by Prof. C. Paul in his long scientific career. The inclusion of parameters variability effects is also considered, and it is demonstrated how statistical simulations can become affordable by means of recently-introduced stochastic methods. Finally, the necessity of practical training of designers is mentioned, and an experience relying on realistic PCB demonstrators is illustrated.

Overview of Signal Integrity and EMC Design Technologies on PCB: Fundamentals and Latest Progress

A cascaded S-parameter method is proposed in this paper for signal/power integrity analysis of multiple vias in a multilayer printed circuit board (PCB). The proposed method enables efficient and accurate construction and simulation of physics-based via model for complex multilayer PCB structures involving vias. The physics-based via model describes the parasitic effects near each via region as well as mutual coupling among different vias. In this model, each via portion between two parallel plates is regarded as a three-port network with two coaxial ports and one radial port between the two plates. A procedure is first developed to obtain the S-parameters of a single plate pair, which combine the three-port via networks with the impedance matrix of the parallel-plate pair. Once the S-parameters of each plate pair are obtained, an assembling technique for cascading microwave networks is further developed. The method proposed in this paper has been validated by both simulations with a commercial circuit simulator and measurements.

Signal/Power Integrity Analysis for Multilayer Printed Circuit Boards Using Cascaded S-Parameters

We propose a generalized T -matrix definition that facilitates the conversion between the S-parameter and T-parameter for multiport networks based on the well understood and mathematically simple two-port relations. This approach generalizes all multiport networks into two cases: balanced and unbalanced. Balanced networks have the same number of entrance and exit ports and are symmetric to the two-port network. Unbalanced networks generate a nonsquare T -matrix and do not have the same number of entrance and exit ports. Through careful selection of the T -matrix, this method extends two-port symmetry to multiport networks and provides an engineering implementable relationship between the S-parameter and T-parameter for multiport networks. This symmetry extension allows a practical means to cascade and de-embed such networks.

Multiport $S$ -Parameter and $T$ -Parameter Conversion With Symmetry Extension

Efforts to reduce high-speed memory interface power have led to the adoption of data bus inversion or bus-invert coding. This study compares two popular algorithms, which seek to limit the number of simultaneously transitioning signals and bias the state of transmitted data toward a preferred binary level, respectively. A new algorithm, which provides a compromise between transition frequency and preferred signal level, is proposed, and the three algorithms are compared in terms of their impact on power consumption, power supply noise reduction, and general signal integrity enhancement when used in conjunction with a variety of link topologies.

Data Bus Inversion in High-Speed Memory Applications

This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3" FR4 PCB channels while achieving power efficiency of 61 mW/Gbps at full speed The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 16-Gbps and 64-Gbps operations, respectively, without package change The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor intersymbol interference (ISI) mitigation In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 25 × energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

The cascading properties of general four-port networks are explored with respect to the standard to mixed-mode transformation of scattering matrices. Rigorous proofs are given to show that, for balanced networks, the odd-/even-mode scattering matrix of two cascaded networks equals the scattering matrix of the cascade of the respective odd-/even-mode networks. This concept is used to extract physical equivalent-circuit models for coupled backplane vias, differential package traces, and differentially routed data pins of XDR memory devices

Properties of mixed-mode parameters of cascaded balanced networks and their applications in modeling of differential interconnects

In this paper, the design, modeling, and analysis methodologies used to develop a 64 Gb/s memory interconnect system using conventional interconnect technologies are presented. The traditional design and development process of the high-speed memory system remains valuable for multi-Gigabit system design. However, the uncertainty in time and voltage of conventional circuit simulation tools can be a significant portion of the bit time and voltage swing, respectively. Therefore, improved modeling and simulation methodologies that are based on fullwave electromagnetic and hardware correlations are a critical part of predicting the performance and verifying the robustness of multi-GHz interconnect systems. The design, modeling and characterization of an XDR system operating at 6.4 Gb/s data rates are presented. The improved modeling and measurement techniques are described. To illustrate the validity of the proposed modeling methodologies, channel models are correlated with actual hardware at both component and system levels in both time and frequency domains. Finally, effects of a simple preemphasis equalization technique are also analyzed.

http://ieeexplore.ieee.org/iel5/9210/29211/01320296.pdf

Design and analysis methodologies of a 6.4 Gb/s memory interconnect system using conventional packaging and board technologies

This paper analyzes the impact of standard and coreless packages on the overall high-speed system performance for data rate beyond 20 Gbps. Instead of focusing on package electrical performance in isolation, we study the package impact on the system performance metrics such as voltage and timing margins and bit error rate (BER) bathtub curves in both time and voltage by employing statistical system simulation methods. Furthermore, the package impact on the quality of the power supply network is also studied using conventional frequency and time domain simulation techniques. Finally, three designs with standard and coreless packages are analyzed to compare the package impacts on signal integrity and power integrity of high-speed systems.

System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps

The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the LQFP package leadframes, power integrity is a major challenge for achieving high data rates. While single-ended signaling systems such as DDR and GDDR are very difficult to operate at multi-gigabit data rates using this highly inductive LQFP package, differential signaling systems such as an XDR memory interface is more immune to supply noise and it is suitable for high data rate operations. In this paper, we demonstrate that the XDR memory system with LQFP memory controller package can operate reliably at 3.2Gb/s. The proposed design is achieved by deploying a package/chip co-design approach, and by carefully balancing the supply-noise-induced jitter on different supply rails of the chip. Finally, the system function is validated under a test system with the proposed LQFP package and the model to hardware correlation at system level is presented.

J. Feng

Papers

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Properties of mixed-mode parameters of cascaded balanced networks and their applications in modeling of differential interconnects

Design and analysis methodologies of a 6.4 Gb/s memory interconnect system using conventional packaging and board technologies

System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps

Design of low cost QFP packages for multi-gigabit memory interface