Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

Preface. Glossary. 1. Introduction to FPGAs. 2. Commercially Available FPGAs. 3. Technology Mapping for FPGAs. 4. Logic Block Architecture. 5. Routing for FPGAs. 6. Flexibility of FPGA Routing Architectures. 7. A Theoretical Model for FPGA Routing. References. Index.

Field-Programmable Gate Arrays

Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic block testing, the configuration of used logic resources remains unchanged, while the interconnect configuration and unused logic resources are modified. Logic testing is performed in only one test configuration whereas interconnect testing is done in a logarithmic number of test configurations. This approach is able to achieve 100% fault coverage

Application-Dependent Testing of FPGAs

This paper presents an FPGA test and coverage methodology. BIST and "shift register" styles of test are discussed. Gate level fault grading results are then presented. Use of an "iterative logic unit" and its impact on test and fault grading is discussed.

FPGA test and coverage

An application-dependent test strategy to be used by an FPGA user is presented which requires only 3 test configurations. In this specific strategy, the interconnect is first tested by modifying the logic block configuration and preserving the interconnect configuration. Then, the used logic blocks are fully tested by modifying the interconnect configuration. Results for some benchmark applications mapped into the Xilinx FPGAs are also provided.

A multi-configuration strategy for an application dependent testing of FPGAs

Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

IS-FPGA : a new symmetric FPGA architecture with implicit scan

This paper studies the test pattern generation problem for FPGA implemented combinational circuits. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of manufacturing-oriented test procedure, application-oriented test procedure and AC-non-redundant fault. Then, the test pattern generation problem is discussed and it is pointed out that a high AC-non-redundant fault coverage can be obtained only by using an adequate FPGA representation. It is also shown that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

J. Figueras

Papers

IS-FPGA : a new symmetric FPGA architecture with implicit scan

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits