In this paper, a review of the developments in MRAM technology over the past 20 years is presented. The various MRAM generations are described with a particular focus on spin-transfer torque MRAM (STT-MRAM) which is currently receiving the greatest attention. The working principles of these various MRAM generations, the status of their developments, and demonstrations of working circuits, including already commercialized MRAM products, are discussed.

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Magnetoresistive Random Access Memory

One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element.

Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM)

Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Method for manufacturing high density non-volatile magnetic memory

In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Method for manufacturing non-volatile magnetic memory

One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof

Blocking temperature written magnetic random access memory element test structures of various sizes and tunnel barrier resistance area products were fabricated in order to study the dependence of writing efficiency and tunnel junction integrity on the thermal environment of the memory element and tunnel junction resistance area product. The test structures were programmed using a CPP writing mode, where the device is heated by passing a small current through the tunnel junction. The device is then field cooled to set the direction of an IrMn/NiFeCo storage layer. Quasistatic write current was measured as a function of resistance area product and for underlayers with differing thermal conductivities. Linear fits to the size dependent write current data suggest that properly designed submicron bits can be written quasistatically at <100 mu A. Write current for a fixed thermal environment was found to depend inversely on resistance product, but too large a resistance area product causes the tunnel barriers to fail before the memory element can be heated above the blocking temperature of the storage layer. In addition, if the thermal conductivity between the magnetic tunnel junction and substrate is too small, the magnetic tunnel junction will fail before the blocking temperature is reached, even at very low resistance area product values. Proper device design should thus optimize cell thermal resistance and tunnel junction resistance for both reliability and minimum power consumption

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Effect of Resistance-Area-Product and Thermal Environment on Writing of Magneto-Thermal MRAM

An analysis has been performed for spin dependent tunneling memory cells with a 5nm thick pinned, storage magnetic layer with a 60nm diam and with a saturation magnetization of 1000emu∕cm3. In reading, the required pinning fields plus anisotropy fields for the cases of with and without error correction were found to be 79 and 108Oe. The required total fields for writing for the cases with and without error correction were calculated to be 93 and 129Oe. The write current needed to provide the total, effective, 129Oe write field was calculated to be 1.1mA for the assumed word line structure. The needed heating current through the tunnel cell was calculated to be 41μA assuming a tunnel junction and an added resistive layer. A multiple sample read mode with an autozero step and a word read field requires word read currents of 2.50 and 2.75mA. The multisample, autozero mode has wider margins. If the semiconductor selection matrix can be placed underneath the cells, the calculated cell is 0.022μm2.

Analysis of 60nm diam spin dependent tunneling memory cells with thermally assisted writing

This work focuses on an experimental study of the effect of the thermal environment and the resistance area product (RA) of an magnetic tunnel junction (MTJ) on the MTJ reliability and minimum required heating current of CPP thermally written magnetic random access memory (MRAM). Proper device design should optimize cell thermal resistance and MTJ RA for both reliability and minimum power consumption.

Effect of Memory Element Resistance-Area-Product and Thermal Environment on Writing of Magneto-Thermal MRAM

The very small and dense SDT memory cells arrays can be achieved with SDT memory cells in which the information is stored in the direction of the IrMn low blocking temperature. To demonstrate the durability and stability of the written IrMn antiferromagnetic pinning, a variety of test were conducted. For simplicity in fabrication, the test were conducted with just spin valve cells rather SDT cells. The high speed writing tests were conducted on a variety of spin valve memory cells with 60 Angstrom thick IrMn pinning. Cells were continuously written up to 10 trillion times with 27 nanosecond write pulses at a 9 MHz rate. The amplitude for the pulses was chosen so a single pulse provided sufficient heating or annealing to reverse the pinning. The measured time constant for heating and cooling of the cells was found to be 9+-2 nanoseconds. The tests on the limited number of samples suggests that the cells can be written indefinitely with adequate performance.

J. G. Deak

Papers

Effect of Resistance-Area-Product and Thermal Environment on Writing of Magneto-Thermal MRAM

Analysis of 60nm diam spin dependent tunneling memory cells with thermally assisted writing

Effect of Memory Element Resistance-Area-Product and Thermal Environment on Writing of Magneto-Thermal MRAM

Thermally Assisted Writing of Cells with IrMn Pinning Using 27 Nanosecond Pulses