In recent years, the study of lightweight symmetric ciphers has gained interest due to the increasing demand for security services in constrained computing environments, such as in the Internet of Things. However, when there are several algorithms to choose from and different implementation criteria and conditions, it becomes hard to select the most adequate security primitive for a specific application. This paper discusses the hardware implementations of Present, a standardized lightweight cipher called to overcome part of the security issues in extremely constrained environments. The most representative realizations of this cipher are reviewed and two novel designs are presented. Using the same implementation conditions, the two new proposals and three state-of-the-art designs are evaluated and compared, using area, performance, energy, and efficiency as metrics. From this wide experimental evaluation, to the best of our knowledge, new records are obtained in terms of implementation size and energy consumption. In particular, our designs result to be adequate in regards to energy-per-bit and throughput-per-slice.

Lightweight Hardware Architectures for the Present Cipher in FPGA

This paper presents a novel FPGA-based design for the lightweight block cipher PRESENT and its implementation results The proposed design allows to study area-performance trade-offs and thus constructing smaller or faster implementations When optimized by area, the proposed design exhibits smaller latency and fewer FPGA resources than representative related works in the literature

Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher

Lightweight cryptography has recently emerged as a strong requirement for any highly constrained connected device; encryption/decryption processes must strike the balance between speed, area, power efficiency, and security robustness. The aim of this paper is to study the potential gains of the lightweight cryptography algorithms compared to the classic ones in hardware implementation. Advanced Encryption Standard (AES) as the standard, PRESENT and the very recently published GIFT are considered along with several optimized hardware versions of each one. Low- and high-security levels with 80- and 128-bit key length respectively are compared. They are all implemented on a Xilinx Kintex-7 FPGA, exploiting different slice configurations to evaluate their performances. The results show the expected benefits in terms of throughput and area, which allows selecting the best lightweight crypto-ciphers depending on the target device or application. In addition, correlation power analysis is performed on each cipher to estimate their resistance against side-channel analysis.

https://hal-lirmm.ccsd.cnrs.fr/lirmm-02081085/document

Evaluation of SPN-Based Lightweight Crypto-Ciphers

Security and privacy are of prime concern in the emerging internet of things (IoT) and cyber-physical systems (CPS) based applications. Lightweight cryptography plays an essential role in securing the data in this emerging pervasive computing environments. In this paper, we propose a high-performance and area-efficient VLSI architecture with 64-bit datapath for the PRESENT block cipher. The proposed architecture performs an integrated encryption/decryption operation for both 80-bit and 128-bit key lengths. The architecture is synthesized for the Virtex-5 XC5VLX110T FPGA device, available on the Xilinx ML-505 platform. It has been observed that the proposed architecture utilizes 0.73% and 0.87% of FPGA slices for 80-bit and 128-bit key lengths, respectively. A throughput of 410 Mbps and power consumption is about 16 mW for both the key lengths.

A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher

Security and privacy of the Internet of Things (IoT) systems are critical challenges in many data-sensitive applications. The IoT systems are constrained in terms of execution time, flexibility and computational resources. In recent years, many encryption algorithms have been proposed to provide the security of IoT communication. In this study, flexible and high-throughput hardware structures of the PRESENT, SIMON, and LED lightweight block ciphers are presented for IoT applications. The proposed flexible structures can perform various configurations of these block ciphers to support variable key sizes. For example, the PRESENT, SIMON, and LED ciphers support key sizes (80, 128 bits), (96, 144, 128, 192, and 256 bits), and (64, 128 bits), respectively. Therefore, these architectures provide versatile implementations that enable adaptive security level using a variable key size. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. In the PRESENT and LED ciphers, the S-boxes are implemented based on area-optimised logic circuits. The implementation results of proposed flexible architectures are achieved in 180 nm CMOS technology. Area, throughput and throughput/area of the proposed structures have improved compared to other related works.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0363

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform Our proposed design uses an 8-bit datapath to reduce hardware size Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping Further factorization is also done to reduce the size of the Boolean S-Box As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform Our design also features a respectable throughput of 5132 Mbps at the maximum frequency of 236574 MHz

J. J. Tay

Papers

Compact FPGA implementation of PRESENT with Boolean S-Box