M
Ming Ming Wong
Researcher at Nanyang Technological University
Publications - 30
Citations - 295
Ming Ming Wong is an academic researcher from Nanyang Technological University. The author has contributed to research in topics: Composite field & Gate count. The author has an hindex of 9, co-authored 27 publications receiving 231 citations. Previous affiliations of Ming Ming Wong include Swinburne University of Technology & Swinburne University of Technology Sarawak Campus.
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Journal ArticleDOI
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes
TL;DR: This work derives three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF(22)2)2 from a sequence of algorithmic and architectural optimization processes.
Proceedings ArticleDOI
Compact FPGA implementation of PRESENT with Boolean S-Box
TL;DR: This work has achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform, and features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.
Proceedings ArticleDOI
A New High Throughput and Area Efficient SHA-3 Implementation
TL;DR: The presented SHA-3 hash implementations employed architectural optimization approaches based on the concepts of unrolling, pipelining and subpipelining which produced a total of five implementations ofSHA-3 which are denoted as Cases I-V in both FPGA and ASIC.
Proceedings ArticleDOI
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip
TL;DR: A lightweight hardware-based secure boot architecture that incorporates an optimized Physical Unclonable Function (PUF) for providing keys to the security blocks of the System on Chip (SoC), among which, secure boot and remote attestation are presented.
Journal ArticleDOI
Composite field GF(((22)2)2) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion
TL;DR: The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes by exploiting algebraic normal form representation followed by a sub-structure sharing optimisation.