We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT) The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set characteristic equation using straightforward but powerful greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point For difficult faults, the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is ten times faster for those networks which have been completed by previous algorithms Our implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms TEGUS combines the advantages of the elegant organization of SAT-based algorithms with the efficiency of structural algorithms

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Combinational test generation using satisfiability

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Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

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* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
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System-on-Chip Test Architectures: Nanometer Design for Testability

Testing the K longest paths through each gate (KLPG) in a circuit detects the smallest local delay faults under process variation. In this work a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate in a combinational circuit is presented. Many techniques are used to significantly reduce the search space. The results on the ISCAS benchmark circuits show that this methodology is very efficient and able to handle circuits with an exponential number of paths, such as c6288.

An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit

We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality.

Segment delay faults: a new fault model

We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.

Line coverage of path delay faults

We propose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called "line delay test", is a path delay test for the longest sensitizable path producing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the number of lines. However, the line delay test criterion resembles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing length are targeted. We present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable for either a rising or falling transition depending on the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. We give results on benchmark circuits.

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On test coverage of path delay faults

The new test pattern generation system for path delay faults in combinational logic circuits considers robust and nonrobust tests, simultaneously. Once a robust test is obtained for a path with a given transition, another test for the same path with the opposite transition is immediately derived with a small extra effort. To facilitate the simultaneous consideration of robust and nonrobust tests, we derive a new nine-value logic system. An efficient multiple backtrace procedure satisfies test generation objectives. We also use a path selection method which covers all lines in the logic circuit by the longest and the shortest possible paths through them. A fault simulator in the system gives information on robust and nonrobust detection of faults either from a given target set or all path faults. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits substantiate the efficiency of our algorithm in comparison to other published results.

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An efficient automatic test generation system for path delay faults in combinational circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.

J. Jacob

Papers

Line coverage of path delay faults

On test coverage of path delay faults

An efficient automatic test generation system for path delay faults in combinational circuits

Multiple fault detection in two-level multi-output circuits

Switching theoretic approach to image compression