A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed.

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Jitter and phase noise in ring oscillators

Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.

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Low-jitter and process independent DLL and PLL based on self biased techniques

http://ieeexplore.ieee.org/iel2/3508/10440/00488539.pdf

FA 8.1: Low-Jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques

A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications It achieves a delay resolution equal to a buffer delay divided by the number of rings The coupling employed forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a buffer delay The buffer stage used in the ring oscillators is based on a source-coupled pair and achieves high supply noise rejection while operating at low supply voltages Experimental results from a 2- mu m N-well CMOS implementation of the delay generator demonstrate that it can achieve an output delay resolution of 101 ps while operating at 141 MHz with a peak error of 58 ps >

/pdf/precise-delay-generation-using-coupled-oscillators-4j4h12kg4n.pdf

Precise delay generation using coupled oscillators

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

Design of high-performance CMOS charge pumps in phase-locked loops

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8- mu m CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency. >

J.K. Greason

Papers

A PLL clock generator with 5 to 110 MHz of lock range for microprocessors