Journal ArticleDOI
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
Ian A. Young,J.K. Greason,J.E. Smith,Keng L. Wong +3 more
- Vol. 27, Iss: 11, pp 1599-1607
TLDR
In this paper, an analog phase-locked loop (PLL) was used for deskewing the internal logic control lock to an external system lock, achieving a clock skew of less than 0.1 ns for a 50-MHz system clock frequency.Abstract:
A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8- mu m CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency. >read more
Citations
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Journal ArticleDOI
Jitter and phase noise in ring oscillators
TL;DR: A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented in this paper, where the impulse sensitivity functions are used to derive expressions for the jitter.
Journal ArticleDOI
Low-jitter and process independent DLL and PLL based on self biased techniques
TL;DR: In this article, a delay-locked loop (DLL) and phase-locked loops (PLL) designs based upon self-biased techniques are presented, which achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and low input tracking jitter.
Journal ArticleDOI
Precise delay generation using coupled oscillators
J.G. Maneatis,Mark Horowitz +1 more
TL;DR: In this paper, a delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with sub-gate delay resolution for chip testing applications, achieving a delay resolution equal to a buffer delay divided by the number of rings.
Proceedings ArticleDOI
Design of high-performance CMOS charge pumps in phase-locked loops
TL;DR: The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.
References
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Journal ArticleDOI
Charge-Pump Phase-Lock Loops
TL;DR: This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
Journal ArticleDOI
A variable delay line PLL for CPU-coprocessor synchronization
M.G. Johnson,E.L. Hudson +1 more
TL;DR: In this paper, a fully integrated phase-locked loop (PLL) is used to time-align the hi-Z/low-Z transitions of a CMOS CPU and its floating-point coprocessor.
Journal ArticleDOI
A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS
B. Kim,D.N. Helman,Paul R. Gray +2 more
TL;DR: In this article, a high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described.
Journal ArticleDOI
An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range
TL;DR: In this article, the depletion-mode linear resistor of Babanezhad and Temes (IEEE J. SC-19, p.932-8, 1984) is implemented in enhancement-mode devices.