Passive RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known a priori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.

Analysis and Design of Passive Polyphase Filters

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV $_{\rm ppd}$ to 1.06 V $_{\rm ppd}$ . RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 $^{-12}$ is 42 mV $_{\rm ppd}$ . The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 $^{-15}$ on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

A down-conversion circuit (30) for a receiver circuit (10) is disclosed, the down- conversion circuit 30 comprises a first passive switching mixer (70) arranged to down-convert a received radio frequency, RF, signal with a first local oscillator, LO, signal (LO1) having a first duty cycle for generating a first down-converted signal at an output port (75) of the first passive switching mixer (70). The down-conversion circuit (30) further comprises a second passive switching mixer (80) arranged to down-convert the received RF signal with a second LO signal (LO2) having the same LO frequency as the first LO signal (LO1) and a second duty cycle, different from the first duty cycle, for generating a second down-converted signal at an output port (85) of the second passive switching mixer (80). In addition, the down- conversion circuit (30) comprises a passive output combiner network (90) operatively connected to the output ports (75, 85) of the first passive switching mixer (70) and the second passive switching mixer (80) and arranged to combine the first and the second down- converted signals such that harmonically down-converted signal content present in the first down-converted signal and harmonically down-converted signal content present in the second down-converted signal cancel in a combined output signal of the down-conversion circuit (30). The passive output combiner network (90) is tunable to adjust magnitudes and phases of the first and the second down-converted signals. A related quadrature down-conversion circuit (50), a related receiver circuit (10), a related communication device (1, 2), and a related calibration method are also disclosed.

Down-conversion circuit

A tunable polyphase filter with integrated input and output buffers was designed and fabricated in a 0.4 /spl mu/m SiGe BiCMOS technology with a 5-6-GHz bandwidth. Series tunable capacitors (varactors) provide phase tunability for the differential quadrature outputs of the polyphase filter. The tunable phase can be used to improve image rejection in Weaver or Hartley architectures, or mitigate in-phase and quadrature (I/Q) phase error in direct conversion or low-IF receivers. The die area of the fabricated circuit with pads is 920 /spl mu/m/spl times/ 755 /spl mu/m. Based on measurements, approximately 15/spl deg/ of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. To the authors' knowledge, this is the first reported tunable I/Q balance polyphase network.

A 5-6-GHz polyphase filter with tunable I/Q phase balance

This paper describes application of a complex band-pass (BP) AE DA modulator to I-Q signal generation for I-Q balance testing of communication IC as well as ATE system usage. First we explain that the complex BP AE DA modulator is superior to two real-BP AE DA modulators regarding to noise-shaping characteristics. Then we examine the characteristics of the complex BP AE DA modulator and its extension — a complex multi-BP modulator — as well as its newly derived Data Weighted Averaging (DWA) algorithm for its linearity enhancement. We also propose a digital self-calibration technique, and show their simulation results. Their combination is also investigated. We discuss application of our proposed techniques to IC testing.

I-Q signal generation techniques for communication IC testing and ATE systems

This paper derives explicit frequency transfer functions for first-, second- and third-order RC polyphase filters (which are important components in analog front-end of wireless transceivers for I, Q signal generation and image rejection) using a concept of complex signal and circulant matrix properties. The results allow us to exploit their characteristics systematically.

J. Kang

Papers

Explicit transfer function of RC polyphase filter for wireless transceiver analog front-end