This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

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VLSI implementations of threshold logic-a comprehensive survey

A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The output produces output NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The threshold switching circuit triggers changes of the output signal state to NULL in response to the states of all the input signals becoming NULL. The threshold switching circuit triggers changes of the output signal state to the meaningful state when the number of the input signals in the meaningful state exceeds a threshold number. The threshold switching circuit triggers changes of the output signal state to the third state when (i) fewer than all input signals are in the NULL state, and (ii) fewer than the threshold number of input signals are in the meaningful state.

Null convention logic system

Complementary MOS (CMOS) devices form a plurality of threshold gate configurations having majority logic functions with near symmetrical switch delay times. Corresponding gate terminals of individual MOS devices within identical N and P channel complementary networks are commonly connected and adapted to receive input signals. Operating voltages are connected to the respective sources of the N and P channel networks and the network drains are commonly connected to provide an output.

Threshold logic using complementary mos device

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL.

Null convention threshold gate

A threshold gate comprising a plurality of complementarysymmetry, field-effect transistor inverters, each inverter receiving at its common gate connection a different input signal and each connected at its output terminal to a common circuit output terminal. The gate may have inputs all of the same weight or, with appropriately chosen values of transistor conduction channel impedance or parallel connected inverters, may have inputs of different weight.

J Lerch

Papers

Threshold gate circuits employing field-effect transistors