scispace - formally typeset
Patent

Threshold gate circuits employing field-effect transistors

TLDR
In this paper, a threshold gate comprising a plurality of complementary symmetry, field effect transistor inverters, each inverter receiving at its common gate connection a different input signal and each connected at its output terminal to a common circuit output terminal.
Abstract
A threshold gate comprising a plurality of complementarysymmetry, field-effect transistor inverters, each inverter receiving at its common gate connection a different input signal and each connected at its output terminal to a common circuit output terminal. The gate may have inputs all of the same weight or, with appropriately chosen values of transistor conduction channel impedance or parallel connected inverters, may have inputs of different weight.

read more

Citations
More filters
Journal ArticleDOI

VLSI implementations of threshold logic-a comprehensive survey

TL;DR: This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades and detail numerous very-large-scale integration (VLSI) implementations including capacitive, conductance/current, and pseudo-nMOS and output-wired-inverters, as well as many differential solutions.
Patent

Null convention logic system

TL;DR: In this paper, a NULL convention logic element comprises an input, an output and a threshold switching circuit, which is used to change the output signal state to the meaningful state when the number of the input signals in a meaningful state exceeds a threshold number.
Patent

Threshold logic using complementary mos device

TL;DR: Complementary MOS (CMOS) devices as mentioned in this paper form a plurality of threshold gate configurations having majority logic functions with near symmetrical switch delay times. Corresponding gate terminals of individual MOS devices within identical N and P channel complementary networks are commonly connected and adapted to receive input signals.
Journal ArticleDOI

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

TL;DR: A new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance is described, based on a design of threshold logic gates and their seamless integration with conventional standard-cell design flow.
Patent

Null convention threshold gate

TL;DR: In this paper, a NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state, and the threshold gate switches its output to the asserted state when the number of asserted inputs exceeds a threshold number.
References
More filters