In the recent past, we have witnessed the adoption of different machine learning techniques for indoor positioning applications using WiFi, Bluetooth and other technologies. The techniques range from heuristically derived hand-crafted feature-based traditional machine learning algorithms, feature selection algorithms to the hierarchically self-evolving feature-based Deep Learning algorithms. The transient and chaotic nature of the WiFi/Bluetooth fingerprint data along with different signal sensitivity of different device configurations presents numerous challenges that influence the performance of the indoor localization system in the wild. This article is intended to offer a comprehensive state-of-the-art survey on machine learning techniques that have recently been adopted for localization purposes. Hence, we review the applicability of machine learning techniques in this domain along with basic localization principles, applications, and the underlying problems and challenges associated with the existing systems. We also articulate the recent advances and state-of-the-art machine learning techniques to visualize the possible future directions in the research field of indoor localization.

A Survey of Machine Learning Techniques for Indoor Localization and Navigation Systems

Passive radio-frequency identification (RFID) systems carry critical importance for Internet of Things (IoT) applications due to their energy harvesting capabilities. RFID-based position estimation, in particular, is expected to facilitate a wide array of location-based services for IoT applications with low-power requirements. In this paper, considering monostatic and bistatic configurations and 3-D antenna radiation pattern, we investigate the accuracy of received signal strength-based wireless localization using passive ultra high frequency RFID systems. The Cramer-Rao lower bound (CRLB) for the localization accuracy is derived, and is compared with the accuracy of maximum likelihood estimators for various RFID antenna configurations. Numerical results show that due to RFID tag/antenna sensitivity, and the directional antenna pattern, the localization accuracy can degrade at blind locations that remain outside of the RFID reader antennas’ main beam patterns. In such cases optimizing elevation angle of antennas are shown to improve localization coverage, while using bistatic configuration improves localization accuracy significantly.

IoT Localization for Bistatic Passive UHF RFID Systems With 3-D Radiation Pattern

A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable large-signal stable (mode-locked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. A 16-oscillator 1.3-GHz distributed clock network in 0.35-??m CMOS is presented here.

Active GHz Clock Network Using Distributed PLLs

Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations. Here, we show that mutually coupled phase-locked loops (PLLs) enable synchronous clocking in large-scale systems with transmission delays. We present a phase description of coupled PLLs that includes filter kernels and delayed signal transmission. We find that transmission delays in the coupling enable the existence of stable synchronized states, while instantaneously coupled PLLs do not tend to synchronize. We show how filtering and transmission delays govern the collective frequency and the time scale of synchronization.

https://iopscience.iop.org/article/10.1088/1367-2630/16/11/113009/pdf

Synchronization in networks of mutually delay- coupled phase-locked loops

This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the whole network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging. Under simple assumptions, these networks of so-called "self-sampled" all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. The main contribution of this paper is a simple design rule that must be met by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific (but important) class of SS-ADPLLs. A synthesis of the different approaches that have been conducted in the study of the synchronization of SS-ADPLLs is also done.

/pdf/synchronization-analysis-of-networks-of-self-sampled-all-45mjs1tgsb.pdf

Synchronization Analysis of Networks of Self-Sampled All-Digital Phase-Locked Loops

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method

/pdf/all-digital-pll-array-provides-reliable-distributed-clock-1c2basbakb.pdf

All-digital PLL array provides reliable distributed clock for SOCs

This paper addresses the problem of the stability and the performance analysis of N-nodes cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions (such as proper filter coefficient values), a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists of analyzing a corresponding linear average system of the cartesian network rather than constructing a piecewise-linear system which is extremely difficult to analyse. The constructed corresponding system takes into account the non-linearity of the network and especially the self-sampling property. It is then analyzed by linear performance criteria such as modulus margin to guarantee a robust stability of the cartesian network. The reliability of our approach is proved by transient simulations in networks of different sizes.

/pdf/a-design-approach-for-networks-of-self-sampled-all-digital-554r6bceza.pdf

A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops

Localization of tagged objects with sufficient precision is a main issue in many industrial applications. In this paper, a new approach is proposed for the localization of UHF passive tags simply using the environment learning approach. This method uses, for a given passive tag located in a 2-D space, an aggregate function of the Received Signal Strength Indicator (RSSI) for all the possible RFID reader's transmission powers. Based on these measurements, we define a location signature, which is compared with those of other tags located at known positions in the neighborhood. We then implement a method based on the k-Nearest Neighbor (k-NN) algorithm to estimate the position of the target tag. Using a realistic test case involving seventy tags and four antennas, we show a very significant improvement of the localization accuracy in comparison with the results obtained using a single RSSI value.

Accurate 2-D localization of RFID tags using antenna transmission power control

This paper deals with the stability of so-called “self-sampled” digital phase-locked-loops (PLLs). These systems are meant to be used as the nodes of autonomous clock distribution networks, where clock signals are locally generated in each node and each node is synchronized with its neighbours. Despite the absence of an absolute reference clock, it is possible to use the local irregular clock to trigger the operations of the digital loop filter. In this paper, we show that, in this mode of operation, PLLs can be modeled as autonomous piecewise-linear systems. We investigate what filter coefficients to choose in order to ensure stability and, hence synchronization. Two methods are explored, the first based on transient simulations, the second on linear matrix inequalities. It is shown that the second method yields much more conservative results than the first but that it cannot apply to all design options of self-sampled PLLs.

/pdf/determination-of-the-behaviour-of-self-sampled-digital-phase-19vurqhyxe.pdf

Determination of the behaviour of self-sampled digital phase-locked loops

RFID has been developed for many applications such as object identification, object traceability, geometric localization, etc. In order to locate an object labeled by a tag, several characteristics of the tag responses have been studied. This yielded theoretical models whose accuracy is not sufficient in practice for targeted applications. In this paper, we investigate how to localize a tag based on the set of received signal strength indicator (RSSI) values measured for a large range of transmission powers. Using an extensive measurement campaign, we establish that the RSSI is a linear function of the transmission power of the RFID reader. Moreover, a minimum transmission power is necessary for activating the tag which also depends on its localization. As a result, the statistics of the RSSI for different transmission powers may be synthetized through a triple. We then show how this triple may be exploited for localizing a tag.

J. M. Akre

Papers

All-digital PLL array provides reliable distributed clock for SOCs

A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops

Accurate 2-D localization of RFID tags using antenna transmission power control

Determination of the behaviour of self-sampled digital phase-locked loops

Towards localization of RFID tags based on experimental analysis of RSSI