In this work the most recent advances in digital image processing techniques has been used to make vehicle drivers face analysis by detecting symptoms of tiredness and distraction in order to prevent sudden risk situations. The results of the experiments show that a large number of car or trucks accidents can be avoided by detecting real-time physical and psychological states of the drivers in normal driving conditions. There are three main objectives in this design: To detect the driver eyelid movements, to detect the number of frames the driver has his eyes closed and to detect when the driver turns right or left (or bows) his head for a long time. Thus, several well known algorithms have been used and optimized for this field of application, such as spatial and temporal filtering, motion detection, optical flow analysis, etc. Digital signal and image processing techniques have been used together. Furthermore, a low-cost real-time solution based upon FPGA (ALTERA FLEX 10K30, field programmable gate array) has been achieved. Moreover, all the laboratory experiments are being carried out on real automobiles and a very low-cost, low-power and real-time solution based on ALTERA Cyclone Device (EP1C3) is available in the short-term.

http://ieeexplore.ieee.org/iel5/9011/28611/01280262.pdf

A low-cost real-time FPGA solution for driver drowsiness detection

A high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 ?m dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in real time, the Loop of an MPEG-2 coder for main profile/main level (MP@ML) resolution when running at 40 MHz. MViP is made up of several specific-purpose units (SPUs), an RISC core processor, banks of internal memory and an optimized crossbar network which lets these pipelined SPUs and RISC core work in parallel at a macroblock-level-pipeline, greatly increasing silicon efficiency.

J. Meneses

Papers

An approach to the design of RISC core processors for VLSI embedded systems