Elmore delay has been widely used to estimate interconnect delays in the performance-driven synthesis and layout of very-large-scale-integration (VLSI) routing topologies. For typical RLC interconnections, however, Elmore delay can deviate significantly from SPICE-computed delay, since it is independent of inductance of the interconnect and rise time of the input signal. Here, we develop an analytical delay model based on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines under step input. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. We observe significant improvement in the accuracy of delay estimates for interconnect trees when compared to the Elmore model, yet our estimates are as easy to compute as Elmore delay. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also illustrate the application of our model in controlling response undershoot/overshoot and reducing interconnect delay through constraints on the moments.

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An analytical delay model for RLC interconnects

This is an overview paper presenting di/dt noise from a designer‘s perspective. Analysis and circuit design techniques are presented taking package parasitics into account. The main focus is on digital CMOS design, but analysis and design suggestions can easily be extended to mixed-mode design.

di/dt Noise in CMOS Integrated Circuits

Ground bounce estimation is important to determine the impact of simultaneous switching of input/output (I/O) drivers and clock drivers on the performance of application-specific integrated circuits (ASIC's). In this paper, we develop models to estimate the peak and damped resonance noise of the ground and power bounce. These models are developed for both long and short channel devices. Comparison with H-simulation program with integrated circuit emphasis (HSPICE) simulation indicates a good match. These models are simple and suitable for hand calculation.

Estimation of ground bounce effects on CMOS circuits

This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the ground bounce, but to distribute it more evenly among the pads while the routing area is kept to a minimum. We first show that proper p/g terminal to pad assignment is necessary to reduce the maximum ground bounce and then present a heuristic for performing simultaneous assignment and p/g net routing. Experimental results demonstrate the effectiveness of our method.

/pdf/multi-pad-power-ground-network-design-for-uniform-2nav2kfn2x.pdf

Multi-pad power/ground network design for uniform distribution of ground bounce

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0/spl plusmn/5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted.

Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits

Design trade-off relations for the last stage of a complementary metal-oxide-semiconductor (CMOS) off-chip driver that meets a prespecified normalized maximum simultaneous switching ground noise and a prespecified normalized time when the switched N-channel metal-oxide-semiconductor transistor (NMOST) leaves the saturation region are provided in this paper. To maintain system performance with control of 90-10% fall time and/or 10-90% rise time, the proposed trade-off relations are then modified numerically for design with prespecified fall/rise time. The proposed trade-offs relate the normalized simultaneous switching noise and the normalized switching time to driver size, load capacitance, ground/power path inductance, number of switching drivers, and input signal rise time. It will be shown that a dimensionless analysis method allows design to be extended to a variety of systems that share the same dimensionless performance. Such a feature will be demonstrated by SPICE simulations of circuits based upon the proposed design relations and MOS1 model, which agrees well with the design goals.

Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

An algorithm is introduced to upgrade package performance for two coupled lines. A compromise between fast response and limited undershoot is based upon a 4% overshoot control condition. It is easy to use this time domain requirement because it can be applied to the transfer function in the frequency domain. In the frequency domain, it is known that a low-frequency approximation to the transfer function provides a simple and accurate trade-off requirement for single-mode overshoot control. For mixed mode, i.e. for the case of one driven line and one quiet line, it is shown here that the same approximation can be used to control the overshoot in the weak coupling case. A closed-form relationship among electrical line and termination parameters results. However, for strong coupling (small line spacing), the time domain transient response with parameters based on the closed-form relationship is inaccurate. For strong coupling it is shown here an average-transfer-function (ATF) method can be used for calculating trade-offs when multiple modes are excited. >

Overshoot control for two coupled RLC interconnections

Guidelines are introduced for designing high-performance interconnections in high-density electronic packages. Three electrical constraints (namely a transient response requirement of the system, an undershoot requirement at the load end of the driven line, and a crosstalk requirement at the load end of the quiet line) relate the design parameters. A simple design algorithm is discussed that relates design parameters. This method is valid for small-capacitive-loads, low-loss lines, and loosely-coupled lines. Ranges for parameters are specified within which the approach is valid. Design curves are presented for this simplified design method. To increase packaging density line cross sections and spacings must be reduced. As a result line loss and line coupling increase. The simple design guidelines presented here show that these trends need not jeopardize circuit performance if s/h/spl ges/0.8 with C/sub L//spl les/0.3 and r/sub D//spl ges/0.45. For systems with parameters outside these ranges, other approaches are needed.

https://ieeexplore.ieee.org/iel4/96/10393/00486507.pdf

Guidelines for high-performance electronic package interconnections-a simple approach

This paper presents a framework for design automation of VLSI interconnect geometries. Crosstalk, overshoot, undershoot, signal delay, and line impedance are design performance parameters under consideration. Since the dependence of electrical performance parameters on geometry is not easily defined, both qualitative and quantitative techniques are used. Two knowledge bases are introduced-a model and simulation base. The model base contains models used for terminations, transmission line parameter extractors, and transmission lines. The simulation knowledge base contains a set of approximations and routines for the exact evaluation of electrical performance parameters. Procedures are introduced for the automatic extraction of applicable models and simulation techniques in the design process. An unconstrained optimization routine is used as a design search technique. The approach presented here gives faster results than approaches shown in literature, with little sacrifice of accuracy.

J.R. Brews

Papers

Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

Overshoot control for two coupled RLC interconnections

Guidelines for high-performance electronic package interconnections-a simple approach

VLSI interconnect design automation using quantitative and symbolic techniques