Abstract An effective solution to enhance the capacity of an optical-interconnect link is utilizing advanced multiplexing technologies, like wavelength-division-multiplexing (WDM), polarization-division multiplexing (PDM), spatial-division multiplexing (SDM), bi-directional multiplexing, etc. On-chip (de)multiplexers are necessary as key components for realizing these multiplexing systems and they are desired to have small footprints due to the limited physical space for on-chip optical interconnects. As silicon photonics has provided a very attractive platform to build ultrasmall photonic integrated devices with CMOS-compatible processes, in this paper we focus on the discussion of silicon-based (de)multiplexers, including WDM filters, PDM devices, and SDM devices. The demand of devices to realize a hybrid multiplexing technology (combining WDM, PDM and SDM) as well as a bidirectional multiplexing technologies are also discussed to achieve Peta-bit optical interconnects.

Silicon-based on-chip multiplexing technologies and devices for Peta-bit optical interconnects

This paper introduces the pixelated wireless optical channel, which transmits data at high rates using a series of coded time-varying images. This multiple-input/multiple-output point-to-point wireless optical channel uses arrays of optical intensity transmitters and detectors to exploit the inherent spatial degrees of freedom and to realize significant gains in spectral efficiency over single-element systems. Spatial discrete multitone modulation is introduced as a means to combat low-pass spatial distortion and to alleviate spatial alignment problems of previous systems. The capacity of pixelated wireless optical channels is estimated by way of a water-pouring spectrum. A proof-of-concept experimental prototype is constructed using a 512times512 pixel liquid crystal display panel and 154times154 pixels of a charge-coupled device camera. A channel model is developed and the capacity estimated to be 22.4 kb/frame. An unoptimized multilevel code and multistage decoder is applied over the spatial frequency bins and shown to yield spectral efficiencies of approximately 1.7 kb/s/Hz over a range of 2 m

A pixelated MIMO wireless optical communication system

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm2.

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A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

The Multiwavelength Assemblies for Ubiquitous Interconnects (MAUI) program is a collaboration between Agilent Laboratories, Palo Alto, CA, and the University of Southern California, Los Angeles, with the goal of enabling fiber-to-the-processor by developing very-high-density optical interconnects and complementary metal-oxide-semiconductor (CMOS) interface electronics. This paper focuses on the parallel wavelength-division-multiplexed optical interconnect technologies and their potential impact on computer systems.

MAUI: enabling fiber-to-the-Processor with parallel multiwavelength optical interconnects

This paper discusses short-distance optical interconnects for general-purpose distributed digital systems. We describe the technology required to optically interconnect elements that are distributed across multiple packaging layers. This includes chips on a board, boards in a backplane, and shelves within a bay. The focus of this paper will be on technology capable of supporting high-data-rate, two-dimensional, optical communication using two-dimensional parallel optical interconnects.

Optical interconnects at the chip and board level: challenges and solutions

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 035-/spl mu/m complementary metal-oxide-semiconductor (CMOS) chip The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate

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J.S. Ahearn

Papers

256-channel bidirectional optical interconnect using VCSELs and photodiodes on CMOS