JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 8, AUGUST 2001 1093
256-Channel Bidirectional Optical Interconnect
Using VCSELs and Photodiodes on CMOS
David V. Plant, Member, IEEE, Michael B. Venditti, Associate Member, IEEE, Emmanuelle Laprise,
Julien Faucher, Member, IEEE, K. Razavi, Marc Châteauneuf, Andrew G. Kirk, Member, IEEE, and J. S. Ahearn
Abstract—Two-dimensional parallel optical interconnects
(2-D-POIs) are capable of providing large connectivity between
elements in computing and switching systems. Using this tech-
nology we have demonstrated a bidirectional optical interconnect
between two printed circuit boards containing optoelectronic
(OE) very large scale integration (VLSI) circuits. The OE-VLSI
circuits were constructed using vertical cavity surface emitting
lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to
a 0.35-
m complementary metal–oxide–semiconductor (CMOS)
chip. The CMOS was comprised of 256 laser driver circuits, 256
receiver circuits, and the corresponding buffering and control
circuits required to operate the large transceiver array. This is the
first system, to our knowledge, to send bidirectional data optically
between OE-VLSI chips that have both VCSELs and photodiodes
cointegrated on the same substrate.
Index Terms—Application-specific integrated circuits (ASICs),
integrated optoelectronics (OEs), optical interconnects.
I. INTRODUCTION
T
WO-DIMENSIONAL parallel optical interconnects
(2-D-POIs) are capable of providing large connectivity
between elements in computing and switching systems [1]–[3].
This interconnect technology is inherently scalable due to
its 2-D format. Optoelectronic very-large-scale integration
(OE-VLSI) circuits that combine the processing power of sil-
icon with the efficiency of GaAs-based emitters and detectors
represent an enabling technology [4], [5]. Specifically, using
heterogeneous integration techniques, large 2-D arrays of ver-
tical cavity surface emitting lasers (VCSELs) and photodiodes
(PDs) can be flip-chip bonded to silicon electronics to provide
optical input–output (I/O) to OE-VLSI application specific
integrated circuits (ASICs) in addition to existing electrical I/O.
Using this technology, we have demonstrated a 256-channel
bidirectional optical interconnect between two printed circuit
boards (PCBs). This paper, which describes these results, is or-
ganized as follows. In Section II, we describe the VCSEL and
PD properties and the heterogeneous integration approach. Sec-
tion III describes the transmitter and receiver circuits. In Sec-
tion IV, we describe the architecture of the chip that was de-
Manuscript received June 12, 2000; revised March 20, 2001. This work was
supported in part by BAE Systems under a contract via the DARPA/ARL VLSI-
Photonics program, DAAL01-98-C-0074, and supported in part by NSERC and
FCAR postgraduate fellowships and the Canadian Institute for Telecommuni-
cations Research under the NCE Program of Canada.
D. V.Plant,M. B. Venditti, E. Laprise, J. Faucher, K. Razavi, M. Châteauneuf,
and A. G. Kirkare with the Department ofElectrical and Computer Engineering,
McGill University, Montréal, QC H3A 2A7, Canada.
J. S. Ahearn is with Informationand ElectronicSystems IntegrationInc., BAE
Systems, NHQ 4-0196, Nashua, NH 03061-0868 USA.
Publisher Item Identifier S 0733-8724(01)05313-0.
signed, fabricated, and successfully operated. Section V is a de-
scription of the PCBs that were used not only for chip testing but
also for demonstrating the optical interconnect. In Section VI,
we describe the optics and optomechanics used to construct the
optical interconnect, and in Section VII, we discuss the exper-
imental results obtained for both the chip and the overall inter-
connect. Section VIII is a conclusion section.
II. OE D
EVICES: VCSELS, PDS, AND HETEROGENEOUS
INTEGRATION
To achieve the OE-VLSI ASIC described in this paper, 2-D
arrays of VCSELs and PDs were fabricated on separate sub-
strates and subsequently integrated onto the silicon complemen-
tary metal–oxide–semiconductor (CMOS) die. In order to sup-
port a compact high-density microoptical interconnect, the VC-
SELs and PDs were interleaved [6]. We describe in this section:
the design and target operating properties of the VCSELs and
PDs, the OE device layout geometries, and heterogeneous inte-
gration techniques including flip-chip bonding and substrate re-
moval of the interdigitated OE devices. This is the first report, to
our knowledge, of the heterogeneous integration of interleaved
VCSELs and PDs on a CMOS substrate.
A. VCSEL and PD Design and Specifications
The VCSELs were proton implanted devices designed to op-
erate at 850 nm with threshold currents of
4.5 mA and slope
efficiencies of 0.25 mW/mA [7]. The devices were also de-
signed to be backside-emitting because of the desire to flip-chip
bond them to CMOS driver circuits as described in Section II-C.
This necessitated removal of the GaAs substrate to minimize
absorption of light. To achieve these objectives, VCSELs were
fabricated with both the n-contact and the p-contact located on
the top surface of the wafer to facilitate electrical contact to the
CMOS circuits. Fig. 1 shows a schematic of the VCSEL geom-
etry indicating emission direction after substrate removaland in-
tegration to the CMOS. The p-contact was formed above the top
distributed Bragg mirror (DBR) and the n-contact was brought
to the substrate surface through mesa isolation and ion implanta-
tion. Fig. 2 is a photomicrograph of four isolated VCSELs prior
to flip-chip bonding and substrate removal; the p-contacts and
n-contacts are indicated. The VCSELs in the photograph are on
a 125-
m 125- m pitch. Once bonded to the CMOS as per
the description given below, the n-contact and DBR became the
top (emitting) surface of the VCSEL.
The PDs were p-i-n structures designed to operate with a
responsivity of 0.5 A/W. Fig. 3 is a photomicrograph of four
isolated PDs on a 125-
m 125- m pitch prior to flip-chip
0733–8724/01$10.00 © 2001 IEEE
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1094 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 8, AUGUST 2001
Fig. 1. A schematic of the VCSEL geometry indicating the emission direction
after substrate removal and integration to the CMOS chip. Based on the partial
transmittivity of the p-contact/DBR, the VCSELs could be probed prior to
hybridization with the CMOS to verify functionality at the wafer level.
Fig. 2. Photomicrograph of four isolated VCSELs prior to flip-chip bonding.
The n-contact and the p-contact are indicated. The scratch marks are a result of
wafer-probing prior to flip-chipping.
Fig. 3. Photomicrograph of four isolated p-i-n’s prior to flip-chip bonding.
The n-contact and the p-contact are indicated.
bonding and substrate removal; the p-contacts and n-contacts
are indicated. The 2-D PD arrays were fabricated at the wafer
level on a 125-
m 125- m pitch and were designed to be
flip-chip bonded to the CMOS driver chip described below in
Section II-C.
B. Optoelectronic Device Layout Geometry
In order to support a compact point-to-point optical inter-
connect system, the VCSELs and PDs were interleaved and ar-
ranged in a clustered geometry [6]. Fig. 4(a) is a schematic of
the free-space microoptic link and Fig. 4(b) shows a schematic
of the VCSEL and PD placement requirements. As is indicated
in Fig. 4(b), VCSELs and PDs were grouped together in clus-
ters, and, within each cluster, rows of VCSELs and PDs were
interleaved. Specifically, a cluster consisted of eight VCSELs
and eight PDs arranged in four rows. The pitch of the optoelec-
tronic devices was 125
m in both the horizontal and vertical di-
rections; therefore, the VCSELs and PDs were on 125-
m hori-
zontal by 250-
m vertical pitch. The complete 256-VCSEL and
256-PD array consisted of 32 clusters arranged in eight rowsand
four columns, as is shown in Fig. 5. The center-to-center spacing
of clusters was 750
m horizontally and 750 m vertically. The
CMOS was designed to accommodate this OE device pitch and
placement.
It is worth noting that both the VCSELs and PDs were fabri-
cated on a 125-
m 125- m pitch at the wafer level in order to
be compatible with typical OE device pitches for 1
prod-
ucts manufactured for the telecommunications industry. The OE
devices, in principle, could be fabricated on a smaller pitch.
During heterogeneous integration, OE devices that did not have
corresponding contact points on the CMOS chip were removed
during the flip-chip bonding and substrate removal processes
described in the next section.
C. Heterogeneous Integration and Substrate Removal
The VCSELs and PDs were integrated onto the CMOS driver
using flip-chip bonding and substrate removal techniques. The
VCSEL flip-chip contact area was 15
m 15 m and the PD
flip-chip contact area was 10
m 10 m. The contact areas
on the CMOS die for the VCSEL driver and PD receiver were
identical to those on the optoelectronic devices.
Heterogeneous integration was accomplished by employing
relatively conventional photolithographic processes to deposit
and lift off contact metals on the wafers followed by a precision
assembly process using a flip-chip bonding tool. In the pho-
tolithographic step, a photoresist polymer is first spun out on
the wafer and printed with the contact metal pattern and then
developed. Indium is then evaporated onto the wafer and the
photoresist is lifted off, leaving metal on the contact pads. This
process was used for the VCSEL and PD wafers and the CMOS
dies. The individual OE device dies were separated by mechan-
ical dicing and then integrated onto a CMOS die using the pre-
cision alignment hybridization tool. The VCSEL die was first
attached to the CMOS chip followed by dry etching to remove
the substrate; integration of the PD die was accomplished next
followedby substrate removal. The bonding of the indium metal
contacts on the CMOS chip and on the OE devices was accom-
plished through a combination of force and controlled temper-
ature. The process resulted in electrical isolation of individual
OE devices and allowed the interleaving of the VCSEL and PD
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PLANT et al.: 256-CHANNEL BIDIRECTIONAL OPTICAL INTERCONNECT 1095
Fig. 4. (a) Schematic of the free-space microoptic link. (b) Schematic of the VCSEL and PD placement requirements.
devices onto a single CMOS die. Although individual dies were
used to assemble this generation of OE-VLSI chips, migration
of the process to the wafer level is relatively straightforward.
Fig. 6 shows a photomicrograph of four clusters after het-
erogeneous integration and substrate removal, each cluster con-
sisting of eight VCSELs and eight PDs hybridized to the under-
lying CMOS chip. This layout geometry proved effective when
designing the architecture of the CMOS circuit discussed in Sec-
tion IV. Fig. 7 is a photograph of the complete OE-VLSI chip
after VCSEL and PD integration. Fig. 8(a) shows a group of four
clusters with 32 VCSELs biased below threshold, and Fig. 8(b)
shows the entire VCSEL array biased above threshold. Using
continuous wave measurements, the VCSEL yield after hetero-
geneous integration was
98%. In the following two sections,
we describe the transceiver circuits and the CMOS chip archi-
tecture which were implemented in this interconnect system.
III. T
RANSMITTER AND RECEIVER CIRCUITS
The main objective of the transceiver circuit design was
to provide enough flexibility to allow for the successful
simultaneous operation of large numbers of transmitters and
receivers. Although simulation results described below indicate
high-speed operation was achievable, high data rate operation
was not a principal design objective. It was expected that the
VCSEL, PD, and CMOS characteristics would vary over a
large device array; thus, the transceiver designs had to allow
for statistical variations in device parameters and had to avoid
dependence on parameters specific to both the silicon and the
OE process [8], [9]. The transceiver circuits were designed to
keep their inherent switching noise generation at a practical
minimum, as well as to be immune to the expected presence
of substantial amounts of aggregate switching noise generated
from a large array of mixed analog and digital circuits.
Given these design objectives, the design of the laser driver
was based on current-steering, as outlined in Fig. 9. Specifically,
a VCSEL was dc-biased with a current
to a point above
the VCSEL threshold current. Modulation current was provided
by the current source
and was steered through either the
VCSEL or through an electrical dummy diode load D1, which
was implemented as a diode-connected PMOS transistor. Cur-
rent steering was achieved with switching transistors M1L and
M1R and complementary rail-to-rail digital CMOS inputs Vin
and Vinb. The polarity of the laser driver circuit was nonin-
verting; thus, when the inputs were logically low (Vin low and
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1096 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 19, NO. 8, AUGUST 2001
Fig. 5. A full view of the VCSEL and PD clustering design. Optical channels 0 and 1 (described in Section IV) are also indicated. Within an individual cluster
and post hybridization, the VCSEL and PD pitch was 125
m in the horizontal direction by 250
m in the vertical direction.
Fig. 6. Four clusters after heterogeneous integration and substrate removal.
The VCSEL device was 110
m
2
112.5
m and had a 20-
m diameter active
region; the p-i-n was 125
m
2
90
m and had a 50-
m
2
50-
m active region.
Vinb high), the VCSEL was biased at and, there-
fore, produced a logically high-output power. When the inputs
were reversed (Vin high and Vinb low), the VCSEL was biased
with only
and produced a logically low output power.
The current-steering nature of the laser driver allowed the
total current drawn from the power supply to remain nominally
constant at
whether the VCSEL was in a high or
low output power state. Power supply current transients could
not be completely eliminated due to the mismatch in electrical
parameters of the dummy load D1 and the VCSEL, but the ap-
proach allowed current transients (
noise) to be kept to a
small fraction of
. The range of currents settable for
and was approximately 6 and 12 mA, respectively. The
Fig. 7. A complete OE-VLSI chip. The rectangular section located in the
middle of the die is the VCSEL and PD array.
nominal voltage supply was 4.8 V. The power dissipation per
laser driver circuit depended on the magnitudes of
and
, and was estimated to be 86.4 mW in the worst case. An
individual transmitter circuit was successfully simulated under
worst-case (i.e., largest magnitude) conditions for
and
at data rates in excess of 1 Gb/s.
The receiver circuit is shown schematically in Fig. 10. It
was optically and electrically single-ended and was based on a
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PLANT et al.: 256-CHANNEL BIDIRECTIONAL OPTICAL INTERCONNECT 1097
(a)
(b)
Fig. 8. (a)Four clusters with 32 VCSEL biased below threshold. (b) The entire
VCSEL array biased above threshold. The distortion is caused by the optical
system used to image the 3-mm
2
6-mm array simultaneously.
common source transimpedance amplifier (TIA) front end [10],
[11]. An offset-control stage was included to compensate for
both the dc-coupled nature of working with CMOS amplifier
stages and the dc-coupled nature of the optical input. This
allowed properties of the receiver such as sensitivity (pream-
plifier feedback resistance) and the accommodation of various
average optical power levels (offset control) to be dealt with
independently, providing greater operational flexibility. The
final stage of the receiver consisted of a Schmitt trigger that
served as a final gain stage for decision-making and provided
some hysteresis in its transfer function to help reduce the effects
of power-supply switching noise in an array environment [12].
As was the case with the laser-driver circuit, the operation of
the receiver was noninverting. If the optical input was logically
high, then the receiver output was also logically high, and vice
versa. Power dissipation for the receiver circuit was dependent
on a multitude of operating conditions such as optical input
power levels and the bias condition of the offset correction
stage. Under typical operating conditions, the power dissipation
per receiver was estimated to be 5 mW. An individual receiver
Fig. 9. Laser driver design.
was successfully simulated at 500 Mb/s with input optical
power levels of 20 and 42
W in the maximum-gain setting
and with 200 and 800
W in the minimum-gain setting.
Via the processes described in Section II-B above, each driver
circuit was integrated with a VCSEL and each receiver was in-
tegrated with a PD; this resulted in a 2-D array of 256 transmit-
ters and receivers. We describe, in the next section, the digital
design and control architecture of the CMOS chip. We also pro-
vide details on the die size and the fabrication technology used
to construct the chip.
IV. CMOS C
HIP ARCHITECTURE
The CMOS chip was designed to act as a network interface
chip for nodes in a computing network [13], [14]. A 32-bit-wide
data bus was a key design goal. To meet these objectives, the
chip was designed using 256 pixels, each pixel being comprised
of a VCSEL hybridized to a laser driver (a transmitter), a photo-
diode hybridized to an amplifier (a receiver), and control logic
to define the operating mode of the pixel. A schematic of a pixel
is shown in Fig. 11.
Referring to Fig. 11, there were four modes of operation
for each pixel: mode 1) electrical data could be transmitted
optically [E-to-O conversion]; mode 2) optical data could be
received electrically [O-to-E conversion]; mode 3) optical data
could be received and retransmitted optically via combinational
logic which resided between receiver and transmitter circuits
[O-to-E-to-O]; and mode 4) received optical data could be
latched in a flip-flop before being resent optically or electri-
cally. In this mode, data could be stored to allow for protocols
which required synchronization.
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