Redundancy of both logic circuits and interconnections is the core principle of both RVLSI (Restructurable or Fault-Tolerant VLSI) and WSI (Wafer Scale Integration). For varying complexity and sizes of circuits different factors of redundancy are required. Effective use of redundancy requires understanding of the failures and failure modes at different stages of the processing and lifetime of VLSI and WSI circuits. This paper consists of two parts. In Part I, sources of failures for MOS devices are discussed. Manifestations of physical failures are described. Use of redundancy for the yield improvement of VLSI circuits is explored through the use of a mathematical model. It is shown that interconnection density and pattern complexities around each section determines the effectiveness of yield improvement. In Part II (to be published in a forthcoming issue), programmable interconnect technologies are described to facilitate restructuring of VLSI and WSI circuits, in this case as they apply to yield improvement through the use of redundancy.

Comments on "Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I&#8212;Sources of failures and yield improvement for VLSI"

The Top-Of-Stack(TOS) register is a high-speed storage which hold the top portion of the frequently used stack entries. We propose a Cut-Back-K algorithm, a sophisticated algorithm for TOS register management, to speed up the stack operation. The performance of this algorithm is analyzed with random-walk model. The effective stack access time with this algorithm can be as fast as the inherent access time of the TOS register in appropriate configurations. The inherent access time of TOSregister formed by on-chip shift register is proportional to O(1)~O(log N) for N cells. On the other hand, N elements arrav of dual-ports register takes O(N 27k) minimum access delay (k:some constant) .

High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis

The complexity of the circuit that can fit on an integrated circuit (IC) chip has reached the level of a million transistors with the advent of Very-large-Scale Integration (VLSI). Several automatic synthesis systems have evolved that "aid" the human designer in managing this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a high-level design specification into a lower level design specification that includes more structural details, leading to the physical design of the IC. The characteristics of ten automatic synthesis systems are summarized.

Automatic hardware synthesis

The supermicros have arrived. Their 32-bit structure-and their performance-quite justifiably earn them the name "micromainframes."

An Architectural Comparison of 32-Bit Microprocessors

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.

The impact of supercomputers on IC technology development and design

A fully integrated 32-bit VLSI CPU chip utilizing 1 /spl mu/m features is described. It is fabricated in an n-channel silicon gate, self-aligned technology. The chip contains about 450000 transistors and executes microinstructions at approximately one per 55 ns clock cycle. It can execute a 32-bit binary integer add in 55 ns, a 32-bit binary integer multiply in 1.8 /spl mu/s, and a 64-bit floating point multiply in 10.4 /spl mu/s. The instruction set provides the functions of an advanced mainframe CPU. Because the implementation of such a complex device poses an organizational as well as a technical challenge, the design philosophy that was adopted is summarized briefly. Careful attention was paid to designer productivity, and design flexibility and testability.

A 32-bit VLSI CPU chip

The design of a fully integrated 32-bit VLSI multiprocessor is outlined. Since this is a high performance design implemented in MOS technology, special system and circuit design tradeoffs have been made to preserve high throughput. These include special packaging, clock generation and system protocols. 2 references.

J.W. Beyers

Papers

A 32-bit VLSI CPU chip

32-bit VLSI system