Digital coherent receivers have caused a revolution in the design of optical transmission systems, due to the subsystems and algorithms embedded within such a receiver. After giving a high-level overview of the subsystems, the optical front end, the analog-to-digital converter (ADC) and the digital signal processing (DSP) algorithms, which relax the tolerances on these subsystems are discussed. Attention is then turned to the compensation of transmission impairments, both static and dynamic. The discussion of dynamic-channel equalization, which forms a significant part of the paper, includes a theoretical analysis of the dual-polarization constant modulus algorithm, where the control surfaces several different equalizer algorithms are derived, including the constant modulus, decision-directed, trained, and the radially directed equalizer for both polarization division multiplexed quadriphase shift keyed (PDM-QPSK) and 16 level quadrature amplitude modulation (PDM-16-QAM). Synchronization algorithms employed to recover the timing and carrier phase information are then examined, after which the data may be recovered. The paper concludes with a discussion of the challenges for future coherent optical transmission systems.

Digital Coherent Optical Receivers: Algorithms and Subsystems

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

This paper summarizes recent trends in the area of low-power A/D conversion. Survey data collected over the past eleven years indicates that the power efficiency of ADCs has improved on average by a factor of two every two years. A closer inspection on the impact of technology scaling is presented to explain the observed trend in the context of shrinking supply voltages and increasing device speed. Finally, a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.

A/D converter trends: Power dissipation, scaling and digitally assisted architectures

We examine analog-to-digital and digital-to-analog converters (ADCs and DACs), as well as digital signal processing (DSP) functions for optical coherent modems.

Advances in High-Speed DACs, ADCs, and DSP for Optical Coherent Transceivers

This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and sampling linearity, while the back-end consists of four ADC arrays, each consisting of 16 10b current-mode non-binary SAR ADCs. The interleaving hierarchy allows for many ADCs to be used per T/H and eliminates distortion stemming from open loop buffers interfacing between the front-end and back-end. Startup on-chip calibration deals with offset and gain mismatches as well as DAC linearity. Measurements show that the prototype ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4 . An estimated sampling clock skew spread of 400 fs is achieved by careful design and layout. Up to 4 GHz an SNR of more than 49 dB has been measured, enabled by the less than 110 fs rms clock jitter. The ADC consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm.

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A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with an array of 2.5 V T/Hs with delay, gain and offset-calibration capability.

J. Wolczanski

Papers

A 24GS/s 6b ADC in 90nm CMOS