Asymmetries in substrate current characteristics due to hot-electron stressing have been observed in short-channel n-MOSFET's. Due to the localized nature of trapped charges or interface traps as a result of hot-electron stressing, transistors can show single-peak or double-hump substrate current characteristics under normal- or reverse-mode measurements. Two-dimensional simulations indicate that a high lateral electric field is generated near the source when the negative charges are trapped there. This electric field is responsible for the observed double-hump substrate current and enhanced gate current injection under reverse-mode measurements for the stressed transistors.

Stress-induced double-hump substrate current in MOSFET's

Measurements of double-hump substrate current and enhanced gate current in funnel-shape (FS) MOSFET's have been recently reported [1]. In this letter an analytical explanation of these observations is given. It is shown that contrary to conventional transistors, the maximum lateral field along the channel of FS transistors operated in the wide-drain mode, and therefore the hot-carrier generation region, is shifted towards the source side as the gate voltage is increased. In addition, the maximum lateral field is increased at high gate voltages, giving rise to the abnormal increase of the substrate current. These results are derived from a simple one-dimensional solution of FS transistor characteristics.

Analytical explanation to double-hump substrate current in funnel-shape transistors

n-channel transistors with a funnel-shape (FS) channel region were fabricated with thin gate oxide (21 nm) and short-channel length (1 µm) to study the effects of channel shapes on hot-electron effects. Two interesting phenomena are observed. First, the double-hump substrate current phenomenon is found when operating with wider channel close to drain side (wide-drain mode), while the narrow-drain mode shows the usual single-peak substrate current characteristics. Second, an enhanced gate current injection is found in the wide-drain mode, which is surprising as substrate current is actually lower in this mode. The finding is interesting as it suggests that floating-gate FS-tranistors with short-channel length and thin gate oxide are more efficient in programming when operating in wide-drain mode. This contradicts the previous SIMOS EPROM device that utilizes funnel-shape channel region operating in narrow-drain mode. The discrepancy is ascribed to the occurrence of double-hump effect in substrate current and associated enhanced gate current injection in FS-transistors when channel length and gate oxide are scaled down.

J.Y. Chen

Papers

Observation of double-hump substrate current in funnel-shape transistors