Showing papers in "IEEE Electron Device Letters in 1985"

An In 0.15 Ga 0.85 As/GaAs pseudomorphic single quantum well HEMT

Abstract: This letter describes high electron mobility transistors (HEMT's) utilizing a conducting channel which is a single In 0.15 Ga 0.85 AS quantum well grown pseudomorphically on a GaAs substrate. A Hall mobility of 40 000 cm2/V.s has been observed at 77 K. Shubnikov-de Haas oscillations have been observed at 4.2 K which verify the existence of a two-dimensional electron gas at the In 0.15 Ga 0.85 As/GaAs interface. HEMT's fabricated with 2-µm gate lengths show an extrinsic transconductance of 90 and 140 mS/mm at 300 and 77 K, respectively-significantly larger than that previously reported for strained-layer superlattice In x Ga 1-x As structures which are nonpseudomorphic to GaAs substrates. HEMT's with 1-µm gate lengths have been fabricated, which show an extrinsic transconductance of 175 mS/mm at 300 K which is higher than previously reported values for both strained and unstrained In x Ga 1-x As FET's. The absence of Al x Ga 1-x As in these structures has eliminated both the persistent photoconductivity effect and drain current collapse at 77 K.

Dependence of channel electric field on device scaling

Abstract: It has been shown previously that the maximum channel electric field E m in a MOSFET is the most important parameter relating to all hot-electron effects and that E m can be represented as ( V_{DS} - V_{DSAT})/l , where l may be regarded as the effective length of the velocity-saturation region. The dependence of l on device geometries and process parameters is investigated in this letter. From both experiment and two-dimensional (2-D) simulation, it is found that E m has a form of ( V_{DS} - V_{DSAT})/ 0.22T\min{ox}\max{1/3}X\min{j}\max{1/2} . Channel length affects the saturation voltage, thus influencing the maximum channel electric field. The scaling of oxide thickness and junction depth, however, often has even greater effects on channel field. This semiempirical model of E m agrees with E m deduced from I SUB within about 5 percent; it can predict I SUB , which has been empirically correlated with hot-electron degradations.

Rapid thermal processing of thin gate dielectrics. Oxidation of silicon

Abstract: A new rapid process for the growth of thin thermal oxide films on crystalline silicon is described. This rapid thermal oxidation (RTO) is performed in a controlled oxygen ambient with the heating provided by tungsten-halogen lamps. The resulting oxides with thicknesses from 40-130 A have a uniformity of better than 2 percent across the 75-mm wafers. Oxidation times at 1150°C vary from 5 to 30 s. Typical breakdown fields of 100-A oxide films were 13.8 MV/cm and typical midgap interface state densities were of the order of 1 × 1010eV-1cm-2. The present RTO films have characteristics equal to or better than furnace grown oxides and because of the short temperature-time cycle they have potential applications for submicrometer VLSI.

Heterojunction bipolar transistor using a (Ga,In)P emitter on a GaAs base, grown by molecular beam epitaxy

Abstract: We report the first N-p-n heterojunction bipolar transistor (HBT) using a (Ga,In)P/GaAs heterojunction emitter on a GaAs base. This combination is of interest as a potential alternate to (Al,Ga)As/GaAs, because of theoretical predictions of a larger valence band discontinuity and a smaller conduction band discontinuity, thus eliminating the need for grading of the emitter/base junction. The structure was grown by molecular beam epitaxy, with the base doping (∼1019cm-3) far exceeding the n-type doping ∼517cm-3) of the (Ga,In)P wide gap emitter (E g = 1.88 eV). Common-emitter current gains of 30 were attained at a current density of 3000 A/cm2, the highest current density achieved without burnout.

Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon

Abstract: n-channel MOSFET's with channel lengths from 75 nm to 5 µm were fabricated in Si using combined X-ray and optical lithographies, and were characterized at 300, 77, and 4.2 K. Average channel electron velocities υ e were extracted according to the equation \upsilon_{e}=g_{mi}/C_{ox} , where g mi is the intrinsic transconductance and C ox is the capacitance of the gate oxide. We found that at 4.2 K the average electron velocity of a 75-nm-channel MOSFET is 1.7 × 107cm/s, which is 1.8 times higher than the inversion layer saturation velocity reported in the literature, and 1.3 times higher than the saturation velocity in bulk Si at 4.2 K. As channel length increases, the average electron velocity drops sharply below the saturation velocity in bulk Si. These experimental results strongly suggest velocity overshoot in a 75-nm-channel MOSFET.

Ultra-shallow high-concentration boron profiles for CMOS processing

Abstract: The fabrication of ultra-shallow high-concentration boron profiles in silicon has been carried out utilizing a XeCl excimer laser. The Gas Immersion Laser Doping (GILD) process relies on a dopant species, in this case diborane (B 2 H 6 ), to be adsorbed on the clean silicon surface and subsequently driven in during a melt/regrowth process initiated upon exposure to the short laser pulse. Secondary Ion Mass Spectrometry and spreading resistance profiles show peak boron concentrations from 5 × 1019cm-3to 5 × 1020cm-3depending on the number of laser pulses, with junction depths from 0.08 to 0.16 µm depending on the laser energy. Electrical characteristics show essentially ideal diode behavior following a 10-s 950°C anneal.

High transconductance InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors

Abstract: Pseudomorphic In 0.15 Ga 0.85 As/Al 0.15 Ga 0.85 As modulation-doped field effect transistors (MODFET's) exhibiting extremely good dc characteristics have been successfully fabricated, dc transconductance in these strained-layer structures of 270 mS/mm were measured for 1-µm gate, normally-on devices at 300 K. Maximum drain current levels are 290 mA/mm, with excellent pinch-off and saturation characteristics. The transconductance increased to 360 mS/mm at 77 K while no persistent photoconductivity or drain collapse was observed. Preliminary microwave results indicate a 300-K current gain cutoff frequency of about 20 GHz. These results are equivalent to the best GaAs/AlGaAs MODFET results and are due in part to the improved transport properties and carrier confinement in the InGaAs quantum well.

Relationship between hot-electrons/Holes and degradation of p- and n-channel MOSFET's

Abstract: The relationship between hot electrons and holes and the degradation of p- and n-channel MOSFET's is clarified by experimentally determining where along the channel the SiO 2 is most affected by each type of carrier. Transconductance degradation is found to be caused by hot-hole injection in pMOSFET's, and by hot-electron injection in nMOSFET's.

Silicon point contact concentrator solar cells

Abstract: Experimental results are presented for thin high resistivity concentrator silicon solar cells which use a back-side point-contact geometry. Cells of 130 and 233 µm thickness were fabricated and characterized. The thin cells were found to have efficiencies greater than 22 percent for incident solar intensities of 3 to 30 W/cm2(30-300 "suns"). Efficiency peaked at 23 percent at 11 W/cm2measured at 22-25°C. Strategies for obtaining higher efficiencies with this solar cell design are discussed.

Analysis and scaling of Kelvin resistors for extraction of specific contact resistivity

Abstract: An accurate numerical analysis of Kelvin resistors used for direct interfacial contact resistance measurements is presented. Curves that allow extraction of true specific contact resistivity from measured specific contact resistivity are given for different ratios of square contact window size (l) to square diffusion tap width (w). Scaling transformations are proposed to extract curves for different feature sizes. It has been shown that when l is made smaller than w, the extracted value of the specific contact resistivity (ρ ce ) can be significantly higher than the true specific contact resistivity (ρ c ), especially for low values of ρ c .

A practical Josephson voltage standard at 1 V

Abstract: A series array of 1484 pairs of Josephson junctions, biased by microwaves at 72 GHz, is demonstrated to provide stable quantized voltages at the 1 V level. The niobium/lead-alloy junctions used in the array are not affected by thermal cycling.

Heavily doped polysilicon-contact solar cells

Abstract: We report the first use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction or back-surface-field (BSF) structure, of silicon solar cells. Compared with BSF and back-ohmic-contact (BOC) control slimples, the polysilicon-back solar cells, show improvements in red spectral response (RSR) and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Three-terminal superconducting device using a Si single-crystal film

Abstract: A three-terminal superconducting device composed of a semiconductor-coupled Josephson junction and an oxide-insulated gate is fabricated. A p-type Si single-crystal film having a 100-nm thickness is used for the semiconductor layer. Two superconducting electrodes of the Josephson junction correspond to source and drain electrodes of the three-terminal device. Josephson tunneling current flows between source and drain electrodes, and is controlled by the gate bias voltage.

Surface superlattice formation in silicon inversion layers using 0.2-µm period grating-gate electrodes

Abstract: Transport has been studied in n-channel metal-oxide-semiconductor field-effect transistors (MOSFET's) in which a 0.2-µm-period tungsten grating, with lines perpendicular to the current flow, was incorporated into the gate. This gate structure, which was fabricated using X-ray lithography and lift-off, produces a controllable periodic modulation of the inversion electron distribution. Low-temperature conductance measurements reveal reproducible structure which is consistent with the formation of a surface superlattice in the inversion layer.

Resonant tunneling transistors with controllable negative differential resistances

Abstract: Three-terminal devices based on resonant tunneling through two quantum barriers separated by a quantum well are presented and analyzed theoretically. Each proposed device consists of a resonant tunneling double barrier heterostructure integrated with a Schottky barrier field-effect transistor configuration. The essential feature of these devices is the presence, in their output current-voltage ( I_{D} - V_{D} ) curves, of negative differential resistances controlled by a gate voltage. Because of the high-speed characteristics associated with tunnel structures, these devices could find applications in tunable millimeter-wave oscillators, negative resistance amplifiers, and high-speed digital circuits.

Antimony and arsenic segregation at Si-SiO 2 interfaces

Abstract: The behavior of shallow Sb and As implants has been investigated in the vicinity of the Si-SiO 2 interface. The implants were performed through thin typically 10-nm oxides and then subjected to inert ambient annealing between 900 and 1000°C. It has been found that the diffusing dopants have an essentially unity sticking coefficient at the SiO 2 interface, until ∼ 2 × 1014/cm2is segregated. All indications are that the segregated Sb/As forms a single monolayer at the interface. The dopants in this layer are electrically inactive. Such a loss of active dopants must be taken into account in the design of submicrometer devices.

Analysis of insulated gate transistor turn-off characteristics

Abstract: A model based upon a MOSFET driving a wide-base p-n-p transistor is presented for analysis of the turn-off behavior of n-channel insulated gate transistors. This model is found to provide a very good quantitative explanation of the shape of the collector current waveform during turn-off. Verification was accomplished using insulated gate transistors (IGT's) fabricated with two voltage ratings and a variety of radiation doses. This analysis allows the separation of the channel (electron) and minority carrier (hole) current flow in the IGT for the first time.

Multiple-channel GaAs/AlGaAs high electron mobility transistors

Abstract: Multiple-channel high electron mobility transistors (HEMT's) have been designed and fabricated on GaAs/AlGaAs heterostructural material grown by molecular beam epitaxy (MBE). The sheet carrier density of the two-dimensional electron gas (2-DEG) measured at 77 K was linearly proportional to the number of high mobility electron channels, and reached 5.3 × 1012cm-2for six-channel HEMT structures. Depletion-mode devices of the double-heterojunction HEMT were operated between negative pinchoff voltage and forward-biased gate voltage without any transconductance degradation. A peak extrinsic transconductance of 360 mS/mm at 300 K and 550 mS/mm at 77 K has been measured for a 1-µm gate-length double-heterojunction enhancement-mode device. An extremely high drain current of 800 mA/mm with a gate-to-drain avalanche breakdown voltage of 9 V was measured on six-channel devices.

A polysilicon emitter solar cell

Abstract: A new solar cell structure is reported in which the emitter consists of a thin layer of in situ phosphorus-doped polysilicon deposited by a low-pressure chemical vapor deposition (LPCVD) techniques. The highest process temperature required to fabricate this structure is only 627°C. Although the use of a polysilicon emitter results in some degradation in blue response, both theoretical and experimental results are presented indicating that photocurrent densities in excess of 30 mA.cm-2are attainable under AM1 illumination. The low back-injection current associated with the polysilicon emitter has allowed a very high open circuit voltage of 652 mV to be obtained at 28°C in a cell illuminated to give a short circuit current density of 30 mA.cm-2.

An induced base hot-electron transistor

Abstract: A novel three-terminal device is proposed in which the base represents an undoped quantum well in a graded-gap heterostructure. The base conductivity is provided by a two-dimensional electron gas induced by the collector field. The intrinsic delay time is estimated to be about 1 ps at room temperature with a common-base current gain close to unity.

Millimeter-wave low-noise high electron mobility transistors

Abstract: High electron mobility transistors (HEMT's) have been fabricated which demonstrate excellent millimeter-wave performance. A maximum extrinsic transconductance as high as 430 mS/mm, corresponding to an intrinsic transconductance of 580 mS/mm, was observed in these transistors. A unity current gain cutoff frequency f T as high as 80 GHz and a maximum frequency of oscillation f_{\max} of 120 GHz were projected for these HEMT's. At 40 GHz, a minimum noise figure of 2.1 dB with an associated gain of 7.0 dB has also been measured. These are the highest f_{T}, f_{\max} , and the best noise performance reported to date. The results clearly demonstrate the potential of HEMT's for millimeter-wave low-noise applications.

A 9-GHz frequency divider using Si bipolar super self-aligned process technology

Abstract: A very high-speed 1/8 frequency divider is fabricated, using Si bipolar super self-aligned process technology (SST), and tested. The circuit consists of three T-connected D-type master-slave flip-flops and buffers. A low voltage swing (225 mV) differential circuit technique is adopted for the first stage T-type flip-flop. The divider is capable of operating at up to 9 GHz with a power dissipation of 554 mW.

Short-channel effects in MOSFET's

Abstract: In this letter we present electrical measurements of threshold voltage on matched transistor pairs which show a channel shortening effect due to the presence of dislocations or metallic precipitates in the device. Such effects could present a limitation on the yield and performance of MOS integrated circuits employing short-channel devices.

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

Abstract: Measurements of emitter resistance have been made on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors, fabricated with or without an interfacial oxide layer. It is found that the emitter resistance of phosphorus-doped transistors is considerably lower than that of arsenic-doped transistors. In addition the presence of a deliberately grown interfacial oxide layer leads to a significant increase in emitter resistance for both arsenic- and phosphorus-doped devices.

Investigation of plasmon-induced losses in quasi-ballistic transport

Abstract: We present an ensemble Monte Carlo (EMC) simulation of the effect of electron-electron (e-e) and electron-plasmon (e-pl) interactions on the transient behavior of electrons under high energy injection conditions. It is shown that, in a situation that closely resembles that obtained in the base of a planar-doped barrier (PDB) transistor, the coulombic interaction severely limits the possibility of ballistic transport.

Memory SEU simulations using 2-D transport calculations

Abstract: An advance in the simulation of a single event upset (SEU) of a static memory is achieved by combining transport and circuit effects in a single calculation. The program SIFCOD [4] is applied to the four transistors of a CMOS SRAM cell to determine its transient circuit response following a very high energy ion hit. Results unique to this type of calculation include determination of relative upset sensitivites and different upset mechanisms for specific area hits, i.e., the OFF p-channel drain, the OFF or ON n-channel drain, etc. The calculation determines the transport variables as a function of time in two-space dimensions for each of the four transistors and provides the nodal voltage and current responses for assessing memory upset conditions.

Microwave performance of 0.25-µm gate length high electron mobility transistors

Abstract: The performance of 0.25-µm gate length high electron mobility transistors (HEMT's) is reported. Devices were fabricated on layers grown by MBE. One of the heterostructures had no undoped AlGaAS spacer layer (wafer A), whereas the other had a 40-A spacer layer (wafer B). The maximum stable gain on both wafers was ∼ 12 dB at 18 GHz. The minimum noise figure measured was 0.60 dB at 8 GHz and 1.3 dB at 18 GHz. Wafer A yielded devices with a unity current gain cutoff frequency f t of 65 GHz whereas wafer B gave an f t of 70 GHz. These results can be attributed primarily to the high quality material, low parasitic resistance, and short gate length.

A modification on "An improved method to determine MOSFET channel length"

Abstract: A brief review of a recent paper [1] describing a method to electrically determine the effective channel length is presented. The method uses a simplifying approximation. By defining some new terms this application can be avoided leading to a new method. Finally, data is presented comparing the two methods for MOSFET's clearly violating the approximation and exemplifying the general applicability of the new method.

Formation of TiN/TiSi 2 /p + -Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

Abstract: A low temperature method of fabricating conductive (3.5 Ω/ sq.) p+/n junction diodes possessing excellent I-V characteristics with reverse-bias leakage less than -3 nA.cm-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV11B + through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N 2 ambient simultaneously forms a 0.36-µm deep p+/n junction and a 0.063-µm thick bilayer of TiN and TiSi 2 with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi 2 and Al.

Realization of n-channel and p-channel high-mobility (Al,GA)As/GaAs heterostructure insulating gate FET's on a planar wafer surface

Abstract: Self-aligned gate by ion implantation n-channel and p-channel high-mobility (Al,Ga)As/GaAs heterostructure insulated-gate field-effect transistors (HIGFET's) have been fabricated on the same planar wafer surface for the first time. Enhancement-mode n-channel (Al,Ga)As/GaAs HIGFET's have demonstrated extrinsic transconductances of 218 mS/mm at room temperature and 385 mS/mm at 77 K. Enhancement-mode p-channel (Al,Ga)As/GaAs HIGFET's have demonstrated extrinsic transconductances of 28 mS/mm at room temperature and 59 mS/mm at 77 K. There are the highest transconductance values ever reported on a p-channel FET device.