International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Summary) The abstract should follow the structure of the article (relevance, degree of exploration of the problem, the goal, the main results, conclusion) and characterize the theoretical and practical significance of the study results. The abstract should not contain wording echoing the title, cumbersome grammatical structures and abbreviations. The text should be written in scientific style. The volume of abstracts (summaries) depends on the content of the article, but should not be less than 250 words. All abbreviations must be disclosed in the summary (in spite of the fact that they will be disclosed in the main text of the article), references to the numbers of publications from reference list should not be made. The sentences of the abstract should constitute an integral text, which can be made by use of the words “consequently”, “for example”, “as a result”. Avoid the use of unnecessary introductory phrases (eg, “the author of the article considers...”, “The article presents...” and so on.)

/pdf/ministry-of-education-and-science-of-the-russian-federation-7m2jn0xnm1.pdf

Ministry of Education and Science of the Russian Federation

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

We apply a model checker to the problem of test generation using a new application of mutation analysis. We define syntactic operators, each of which produces a slight variation on a given model. The operators define a form of mutation analysis at the level of the model checker specification. A model checker generates countersamples which distinguish the variations from the original specification. The countersamples can easily be turned into complete test cases, that is, with inputs and expected results. We define two classes of operators: those that produce test cases from which a correct implementation must differ, and those that produce test cases with which it must agree. There are substantial advantages to combining a model checker with mutation analysis. First, test case generation is automatic; each countersample is a complete test case. Second, in sharp contrast to program-based mutation analysis, equivalent mutant identification is also automatic. We apply our method to an example specification and evaluate the resulting test sets with coverage metrics on a Java implementation.

Using Model Checking to Generate Tests from Specifications | NIST

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

Design and Test Technology for Dependable Systems-on-Chip

..................................................................................................... 90 KOKKUVÕTE .................................................................................................. 92 ACKNOWLEDGEMENTS ............................................................................... 94 Appendix A ........................................................................................................ 95 Appendix B ...................................................................................................... 103 Appendix C ...................................................................................................... 109 Appendix D ...................................................................................................... 117 Appendix E ...................................................................................................... 125 Appendix F ...................................................................................................... 133

Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC

The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to extend the use of test configurations for diagnosis purposes and to propose a method for locating faults in the NoC interconnection infrastructure. Additionally, a new concept of functional switch faults, called link faults, is introduced. The approach is well scalable (complexity is square root of the number of switches) and it is capable of unambiguously pinpointing the faulty links inside the switching network.

Test Configurations for Diagnosing Faulty Links in NoC Switches

Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose Designfor- Testability (DfT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults, opens and shorts between adjacent interconnection lines are covered by the method. The approach allows to reach higher fault coverages in comparison to the recent DfT based solutions.

An External Test Approach for Network-on-a-Chip Switches

The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by high-level constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.

Jaan Raik

Papers

Design and Test Technology for Dependable Systems-on-Chip

Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC

Test Configurations for Diagnosing Faulty Links in NoC Switches

An External Test Approach for Network-on-a-Chip Switches

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations