Recently, the number of high-definition media devices such as 8K ultra high-definition (UHD) TV and virtual reality (VR) is rapidly increasing. These multimedia systems require higher data rates for high resolution and versatility. With this increasing technical trend, high-speed connectors and cables are also becoming important. In this paper, we propose a highspeed connector that can transmit high-speed media data. The previous connectors have focused only on a physical connection and a mechanical reliability. However, as the data rate is increased, electrical performances of the connector have also become highly important. Therefore, signal integrity (SI) analysis for insertion loss, attenuation-to-crosstalk ratio (ACR), and impedance mismatch become essential for the high-speed connector. For verification, the 3D EM simulation tool is used to compare the performance of the previous and proposed connector. In conclusion, the proposed high-speed connector has better electrical performances than that of the previous connector.

Design and verification of a high-speed connector for multi-media system

Recently, various high-speed connectors are used for the data transmission. With the high data rate, it is important to design the high-speed connectors considering not only mechanical but also electrical characteristics. In this paper, we propose a 10 Gbps USB 3.2 Gen 2 Type-C connector for TV set-top box. For the high-speed data transmission, the signal integrity (SI) including characteristic impedance, insertion loss and return loss should be considered. We verified the improved SI performance of proposed connector based on time-domain and frequency domain simulation using 3-D electromagnetic (EM) solver. Furthermore, with the proposed connector design, it shows superior SI characteristics at 20 Gbps which is expected to next generation connector’s data rate.

Design and Analysis of a 10 Gbps USB 3.2 Gen 2 Type-C Connector for TV Set-Top Box

Motivated by the increasing market demand for the high performance mobile devices, both the data rate and the number of pin of mixed-signal systems keep on increasing to realize multifunctional yet compact system designs. With this ascending technical trend, many signal integrity (SI) and power integrity (PI) problems such as ISI, jitter, crosstalk, simultaneous switching noise (SSN) have arisen that need to be thoroughly analyzed and tested. In order to accurately monitor the data signals of LPDDR4, a carefully designed test interposer considering such factors as impedance matching, minimization of skew and crosstalk needs to be proposed. In this paper, a novel test interposer scheme composed of a test interposer and silicone rubber sheets is proposed for LPDDR4 memory test. Through a series of simulations and measurements, we experimentally verify the proposed structures in time and frequency domains, and prove their accuracy and practicality.

Jaemin

Papers

Design and analysis of silicone rubber-based TERAPOSER for LPDDR4 memory test