S
Sumin Choi
Researcher at KAIST
Publications - 44
Citations - 288
Sumin Choi is an academic researcher from KAIST. The author has contributed to research in topics: Interposer & High Bandwidth Memory. The author has an hindex of 8, co-authored 44 publications receiving 223 citations.
Papers
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Journal ArticleDOI
Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis
Daniel H. Jung,Youngwoo Kim,Jonghoon J. Kim,Heegon Kim,Sumin Choi,Yoon-Ho Song,Hyun-Cheol Bae,Kwang-Seong Choi,Stefano Piersanti,Francesco de Paulis,Antonio Orlandi,Joungho Kim +11 more
TL;DR: In this article, the authors proposed a noninvasive defect analysis method for high-speed TSV channel with designed and fabricated test vehicles, and the proposed method is demonstrated with time-domain reflectometry measurement results.
Journal ArticleDOI
Signal Integrity Design and Analysis of Silicon Interposer for GPU-Memory Channels in High-Bandwidth Memory Interface
Kyungjun Cho,Youngwoo Kim,Hyunsuk Lee,Heegon Kim,Sumin Choi,Jinwook Song,Subin Kim,Junyong Park,Seongsoo Lee,Joungho Kim +9 more
TL;DR: It is shown that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate and proposed concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s are proposed.
Proceedings ArticleDOI
Design optimization of high bandwidth memory (HBM) interposer considering signal integrity
Kyungjun Cho,Hyunsuk Lee,Heegon Kim,Sumin Choi,Youngwoo Kim,Jaemin Lim,Joungho Kim,Hyungsoo Kim,Yong-Ju Kim,Yunsaing Kim +9 more
TL;DR: Not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.
Proceedings ArticleDOI
Design and Analysis of Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module
TL;DR: In order to suppress SSN, a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance is suggested which successfully shows the suppression of SSN.
Proceedings ArticleDOI
Power distribution network (PDN) design and analysis of a single and double-sided high bandwidth memory (HBM) interposer for 2.5D Terabtye/s bandwidth system
TL;DR: In this article, a single-and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV).