This paper introduces two graph theoretic models that provide a uniform procedure for analyzing 2n-input/2n-output Multistage Interconnection Networks (MIN's), implemented with 2-input/2-output Switching Elements (SE's) and satisfying a characteristics called the "buddy property." These models show that all such n-stage MIN's are topologically equivalent and hence prove that one MIN can be implemented from integrated circuits designed for another MIN. The proposed techniques also allow identical modeling and comparison of permutation capabilities of n-stage MIN's and other link-controlled networks like augmented data manipulator and SW Banyan Network and hence, allows comparison of their permutation. In the case of any conflict in the MIN, an upper bound for the required number of passes has been obtained.

Graph Theoretical Analysis and Design of Multistage Interconnection Networks

Intelligent Co-Pilot Systems (ICPS) offer the next challenge to vehicle-highway automation. The key to ICPSs is the detection of moving objects (other vehicles) from the moving observer using a visual sensor. The aim of the work presented in this thesis was to design and implement a feature detection and tracking strategy that is capable of tracking image features independently, in parallel, and in real-time and to cluster/segment features utilising the inherent temporal information contained within feature trajectories. Most images contain areas that are of little or no interest to vision tasks. An attentive, data-driven, approach to feature detection and tracking is proposed which aims to increase the efficiency of feature detection and tracking by focusing attention onto relevant regions of the image likely to contain scene structure. This attentive algorithm lends itself naturally to parallelisation and results from a parallel implementation are presented. A scene may be segmented into independently moving objects based on the assumption that features belonging to the same object will move in an identical way in three dimensions (this assumes objects are rigid). A model for scene segmentation is proposed that uses information contained within feature trajectories to cluster, or group, features into independently moving objects. This information includes: image-plane position, time-to-collision of a feature with the image-plane, and the type of motion observed. The Multiple Model Adaptive Estimator (MMAE) algorithm is extended to cope with constituent filters with different states (MMAE2) in an attempt to accurately estimate the time-to-collision of a feature and provide a reliable idea of the type of motion observed (in the form of a model belief measure). Finally, poor state initialisation is identified as a likely prime cause for poor Extended Kalman Filter (EKF) performance (and hence poor MMAE2 performance) when using high order models. The idea of the neurofuzzy initialised EKF (NF-EKF) is introduced which attempts to reduce the time for an EKF to converge by improving the accuracy of the EKF's initial state estimates.

Attentive visual tracking and trajectory estimation for dynamic scene segmentation

Two hardware mechanisms are mainly used for data sharing among processing elements in multiprocessors: message passing in loosely coupled multiprocessors and shared memory in tightly coupled multiprocessors. The former has communication overhead and the latter has shared memory contention. Moreover, in image processing, inefficient data input and output schemes are also limitations on performance. In this paper, Flexibly (Tightly/Loosely) Coupled Multiprocessors (FCM) for image processing are proposed in order to alleviate these disadvantages. A variable space memory scheme , in which a set of adjacent memory modules can be merged by a dynamically partitionable bus, is proposed to realize FCM. These architectures are quantitatively analyzed and simulated on the iPSC/1 (Intel's Personal SuperComputer), a hypercube multiprocessor. Parallel algorithms for region labeling and median filtering are simulated on the proposed architectures. The performance of FCM shows remarkable improvement over that of iPSC/1.

Flexibly Coupled Multiprocessors for Image Processing.

Flexibly coupled multiprocessors for image processing

Analysis of dynamic scenes to obtain motion parameters, structures and identities of the objects present in the scene and/or descriptions of the events taking place in the scene is an important problem in machine vision. Dynamic scene analysis involves processing and analysis of a sequence of image frames (snapshots of the scene) taken at a regularly spaced time interval. Since a large volume of data is to be processed, dynamic scene analysis techniques are, in general, computationally very intensive which makes them unsuitable for applications which require real-time response. A common approach to obtaining motion related information about a scene involves analyzing the characteristics of the connected regions in the corresponding difference pictures. Previous implementations of the difference-picture-based technique use multicomputer and multiprocessor systems which are uneconomical because of the overheads involved. In this paper, we propose a VLSI architecture that exploits the pipelining and the parallelism possible in the above technique. Each processor is organized as a multistage linear pipeline and the processor architecture is simple enough that the motion detection and classification system can be implemented as a single VLSI chip. Once the difference picture has been generated and segmented into separate regions corresponding to motions of different objects, each processor in our proposed chip will independently analyze a different region to classify the type of motion occuring in that region within the scene. Currently, the processor architecture is being laid out in silicon at the University of South Florida for actual fabrication and testing. The chip is expected to operate at the rate of 20 MHz.

A VLSI architecture for dynamic scene analysis

In this paper we introduce the concept of pseudoparallelism, in which the serial algorithm is partitioned into several noninteractive independent subtasks so that parallelism can be used within each subtask level. This approach is illustrated by applying it to a real-time dynamic scene analysis. Complete details of such a pseudoparallel architecture with an emphasis to avoid interprocessor communications have been worked out. Problems encountered in the course of designing such a system with a distributed operating system (no master control) have been outlined and necessary justifications have been provided. A scheme indicating various memory modules, processing elements, and their data-path requirements is included and ways to provide continuous flow of partitioned information in the form of a synchronized pipeline are described.

Jain

Papers

A Pipelined Pseudoparallel System Architecture for Real-Time Dynamic Scene Analysis