The manufacture of smaller, faster, more efficient microelectronic components is a major scientific and technological challenge, driven in part by a constant need for smaller lithographically defined features and patterns. Traditional self-assembling approaches based on block copolymer lithography spontaneously yield nanometer-sized hexagonal structures, but these features are not consistent with the industry-standard rectilinear coordinate system. We present a modular and hierarchical self-assembly strategy, combining supramolecular assembly of hydrogen-bonding units with controlled phase separation of diblock copolymers, for the generation of nanoscale square patterns. These square arrays will enable simplified addressability and circuit interconnection in integrated circuit manufacturing and nanotechnology.

https://science.sciencemag.org/content/sci/322/5900/429.full.pdf

Evolution of Block Copolymer Lithography to Highly Ordered Square Arrays

The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (1012 to 1013 cm–2), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (∼10–9 Torr) yields three times lower RC than under normal conditions, reaching 740 Ω·μm and specific contact resistivity 3 × 10–7 Ω·cm2, stable for over four months. Modeling reveals separate RC contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ∼35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the “14 nm” technology node.

Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

https://science.sciencemag.org/content/sci/361/6400/387.full.pdf

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

The continued physical feature size scaling of complementary metal oxide semiconductor (CMOS) transistors is experiencing asperities due to several factors, and it is expected to reach its boundary at size of 22 nm technology by 2018 This paper discusses and analyzes the main challenges and limitations of CMOS scaling, not only from physical and technological point of view, but also from material (eg, high-k vs low-k) and economical point of view as well The paper also addresses alternative non-CMOS devices (ie, nanodevices) that are potentially able to solve the CMOS problems and limitations

/pdf/why-is-cmos-scaling-coming-to-an-end-3anjiqnice.pdf

Why is CMOS scaling coming to an END

SUMMARY AND CONCLUSIONS Scaling CMOS to and beyond the 22-nm technology node(requiring a physical gate length of 9-nm or less) will probablyrequire the introduction of several new material and struc-tural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs. Material changes willinclude strained silicon n- and p-channels and a new gatestack including a high-k dielectric and a metal gate electrode.Structural changes could include fully depleted UTB SOI sin-gle-gate MOSFETs, perhaps followed by fully depleted UTBdouble-gate structures. Attaining the performance require-ments for the final node for high performance applicationscould further require channels providing quasiballistic carriertransport, or very low-resistance source/drain contacts provid-ed by Schottky metal electrodes. The materials and structuralchanges actually introduced to advanced process technologieswill depend both on their readiness for manufacture and theirvalue in improving performance in the ultra-scaled devices.For example, a high-

/pdf/toward-the-introduction-of-new-materials-and-structural-5checsrym5.pdf

James A. Hutchby

Papers

Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance

The road to the end of cmos scaling