An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (28) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.

Semiconductor device having a wire bond pad and method therefor

A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

Serial bus interface system for data communication using two-wire line as clock bus and data bus

In a digital communications system comprising a plurality of modules plugged into slots, the backplane provides a private five-conductor data bus for each module slot so that data from the modules are transmitted over separate busses. Each of the data busses is split into separately driven branches extending to the right and to the left of its corresponding module, so that the drivers are located at the ends of the branches rather than connected to an intermediate point on a bus. Pairs of slots are connected through the backplane so that, instead of having one module in each slot driving a five conductor data bus, the system can alternatively have a double-bandwidth module in every other slot driving a ten-conductor data bus made up of two five-conductor busses. Clock and synchronization signals provided by control modules are conducted to device modules over separate conductors on the backplane. The synchronization signals are encoded to represent the time within each message frame, thereby permitting synchronization within a time as short as twenty microseconds in a two millisecond frame. Reset signals for the individual modules are appended to the synchronization signals. Coordinated switch-over between two redundant control modules is effected by three voting lines controlled respectively by each control module and by all of the device modules ORed together.

Bus architecture for digital communications

An in-line SCSI bus isolation circuit includes two ports for transparently communicating bidirectional data and controls signals therebetween during normal operation using respective dedicated sets of line drivers which may be data bit-by-bit and control signal-by-signal selectively enabled and disabled to permit the bidirectional transparent SCSI communications, and which may be completely disabled to electrically isolate a connected SCSI device on a first SCSI port from the other remaining connected SCSI components on the second SCSI port, so that that device may be removed or inserted onto the SCSI bus at the first port when the line drivers are disabled to prevent the voltage transient signals generated on the first SCSI port from being propagated to the second SCSI port connected to the other SCSI components prior to enabling the line drivers and bidirectional SCSI communications between the two SCSI ports.

In-line SCSI bus circuit for providing isolation and bi-directional communication between two portions of a SCSI bus

A very high speed data bus system for communication among the various functional units that may constitute a large computer system. The bus communication medium comprises a number of line pairs on the backplane, and the bus system comprises a bus control unit for arbitrating requests from a plurality of interface units or ports, there being one such port associated with each functional unit. The functional units are densely packed, that is, mounted in immediately adjacent connectors to define a populated section of the backplane in which all connectors have ports coupled thereto, and one or two unpopulated sections of the backplane in which the connectors are empty. In the populated section, the effective characteristic impedance, designated Z 0 ', is lower than the effective characteristic impedance, designated Z 0 , in the unpopulated region. A populated end of the transmission line is resistively terminated with a resistance corresponding to Z 0 ' while the unpopulated end is terminated with a resistance corresponding to Z 0 . The border between the populated and unpopulated sections is terminated with a resistance corresponding to 1/(1/Z 0 '-1/Z 0 ), designated Z 0 ", thus eliminating signal reflections that could compromise data integrity and degrade system performance. The two lines that define each differential line pair may be effectively crossed over between successive connectors on the backplane so that an individual line is connected alternately to the positive and negative receiver input terminals at successive ports. Driver gating circuitry responsive to first and second data input signals, an enable signal, and a conditional inversion input signal performs multiple levels of gating with a minimum of propagation delay. The preferred differential receiver amplifies a relatively low level differential input signal and performs an exclusive OR function with a conditional inversion signal with a minimum propagation delay between the signal input and an output line pair.

Improved terminator for high speed data bus

High density time division busses suffer from many problems, one of which is that impedance discontinuities (LO, CB; Fig. 10) cause signal reflections to occur along the bus. These reflections, in turn, affect the settling time and noise margins of the bus and thus reduce the time "window" in which valid signals may be received. There is disclosed a transmission bus structure (Fig. 12) which allows for bidirectional, multi-port operation by using current drivers (Do/, D1, D3) instead of the traditional voltage drivers for placing data signals on the bus (Lo/, L1, L3). The transmission bus is designed in a manner which allows transmission and reception from a signal clock (501; Fig. 5) on the same clock edge, thereby substantially increasing the time allowed for transmission response and also simplifying the clock distribution requirements (Fig. 12).

James Dennis Bryan

Papers

Distributed time division multiplexing bus

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