J
James H. Scheuneman
Researcher at Unisys
Publications - 12
Citations - 286
James H. Scheuneman is an academic researcher from Unisys. The author has contributed to research in topics: Parity bit & Stack register. The author has an hindex of 9, co-authored 12 publications receiving 286 citations.
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Patent
Pipelined split stack with high performance interleaved decode
TL;DR: In this article, the authors propose a virtual first-in-first-out stack structure with a data stack and a split control stack, which is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored.
Patent
Memory access system for pipelined data paths to and from storage
TL;DR: In this paper, a pipeline control system is proposed for simultaneously processing request for access to a plurality of memory banks. But the pipeline control does not resolve conflict between plurality request and single request.
Patent
Fault capture/fault injection system
TL;DR: In this article, a hierarchical fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal, and a programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a faulty signal and logging the fault location in a memory for later readout by a maintenance processor or the like.
Patent
Pipelined data stack with access through-checking
TL;DR: In this article, a virtual stack structure utilizing Write Pointers and Read Pointers for providing pipelined data words on a first-in first-out basis to a memory structure is described.
Patent
Error correction check during write cycles
TL;DR: In this article, an error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines.