Storage virtualization systems and methods that allow customers to manage storage as a utility rather than as islands of storage which are independent of each other. A demand mapped virtual disk image of up to an arbitrarily large size is presented to a host system. The virtualization system allocates physical storage from a storage pool dynamically in response to host I/O requests, e.g., SCSI I/O requests, allowing for the amortization of storage resources through a disk subsystem while maintaining coherency amongst I/O RAID traffic. In one embodiment, the virtualization functionality is implemented in a controller device, such as a controller card residing in a switch device or other network device, coupled to a storage system on a storage area network (SAN). The resulting virtual disk image that is observed by the host computer is larger than the amount of physical storage actually consumed.

Storage virtualization system and methods

A buffered peripheral system comprises a backup memory and a primary control unit which has a buffer memory for temporarily storing a copy of the contents of a buffer memory which stores data to be written to a peripheral device and a control device for issuing a command necessary to write the block stored in the buffer memory device to the peripheral device. The primary control unit also includes a recording device for recording the block number corresponding to the block which was most recently written to the peripheral device. The blocks of data which have been written to the peripheral device is then deleted from the backup memory to make room for storing further blocks of data. The system further has a backup control unit substantially identical to the primary control unit. Only the primary control unit normally operates to control the writing to the peripheral device. Upon detection of the failure of the buffer memory in the primary control unit, the backup control unit completes the operation of writing to the peripheral device by retrieving the blocks of data to be written to the peripheral device from the backup memory device using the block number information.

Buffered peripheral system and method for backing up and retrieving data to and from backup memory device

A method and apparatus for transferring data between two storage media, and is used in an illustrative embodiment to transfer data between two storage media in a shadow set, the storage media being accessible to one or more host processors. The method of the preferred embodiment includes the steps of: A. receiving a command from one of the host processors, the command specifying data to be transferred from a first storage medium to a second storage medium; B. transferring the data specified in the command received from the host from the first storage medium to the second storage medium in a series of subtransfers, each of the subtransfers transferring a portion of the data; and C. processing one or more I/O requests to the shadow set received from one or more host processors by, for each received I/O request: a. implementing the I/O request if the I/O request does not involve a section of the shadow set currently involved in one of the subtransfers; and b. stalling the I/O request if the I/O request involves a section of said shadow set currently involved in one of the subtransfers, and implementing the I/O request when the subtransfer has completed.

Transferring data in a digital data processing system

A method, system, and apparatus for accessing a plurality of storage devices in a storage area network (SAN) as network attached storage (NAS) in a data communication network is described A SAN server includes a first interface and a second interface The first interface is configured to be coupled to the SAN The second interface is coupled to a first data communication network A NAS server includes a third interface and fourth interface The third interface is configured to be coupled to a second data communication network The fourth interface is coupled to the first data communication network The SAN server allocates a first portion of the plurality of storage devices in the SAN to be accessible through the second interface to at least one first host coupled to the first data communication network The SAN server allocates a second portion of the plurality of storage devices in the SAN to the NAS server The NAS server configures access to the second portion of the plurality of storage devices to at least one second host coupled to the second data communication network

System and method for accessing a storage area network as network attached storage

A facility is provided for storing in a backup memory only those blocks of a file, or disk partition, which differ from corresponding blocks forming an earlier version of the file. Specifically, a file is divided into a number of blocks and a "signature" is generated for each such block. A block is then stored in the backup memory only if its associated signature differs from a signature generated for an earlier version of the block. In addition, if two blocks of the current version of the file have identical signatures and are to be stored in the backup memory, then only one of the two blocks is stored in the memory and a simple message indicating that the other block is equal to the one block is stored in the memory for the other block. Further, the application of such signatures is advantageously applied to the opposite case of restoring a file using copies of previous versions of the file that are stored in the backup memory.

Incremental computer file backup using check words

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks. Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and started.

Memory back-up system

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors. Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.

Modular computer system

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element At a context switch, the stored information is sequentially written to two separate main memory units A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element The storage operations are carried out by high-speed hardware which stores only the modified data blocks Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and started

Memory back up system with one cache memory and two physically separated main memories

Circuitry for a fault-tolerant computer is disclosed which circuitry is constructed in two identical halves. Each half, by itself, is not a functionally-complete circuit, however, the two identical halves can be connected together to provide a functionally-complete circuit. Each of the two circuit halves is considerably less complex than a functionally-complete circuit yet, when connected together, the two halves provide fault detection capabilities equivalent to a computer system in which the outputs of two functionally-complete, redundant circuits are compared to detect faults. In particular, each inventive circuit half contains a complete data processing and control unit but only one half of the memory which is necessary for a functionally-complete unit. The processing units on each circuit half operate simultaneously on identical data and the same address information is provided to the memories on each circuit half. To provide error detection, address information and data sent from each control unit to its associated memory is compared between circuit halves. In addition, information provided to the circuits over an external bus or generated by the control unit is encoded with an error-detecting code.

Self-checking computer circuitry

A data system architecture is described that allows multiple processing and storage resources to be connected to multiple clients so as 1) to distribute the clients' workload efficiently across the available resources; and 2) to enable scaleable expansion, both in terms of the number of clients and in the number of resources The major features of the architecture are separate, modular, client and resource elements that can be added independently, a high-performance cross-bar data switch interconnecting these various elements, separate serial communication paths for controlling the cross-bar switch settings, separate communication paths for passing control information among the various elements and a resource utilization methodology that enables clients to distribute processing or storage tasks across all available resources, thereby eliminating “hot spots” resulting from uneven utilization of those resources

James M. Nolan

Papers

Memory back-up system

Modular computer system

Memory back up system with one cache memory and two physically separated main memories

Self-checking computer circuitry

Method and apparatus for implementing high-performance, scaleable data processing and storage systems