Patent
Memory back up system with one cache memory and two physically separated main memories
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TLDR
In this article, a non-write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element at a context switch, the stored information is sequentially written to two separate main memory units.Abstract:
Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element At a context switch, the stored information is sequentially written to two separate main memory units A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element The storage operations are carried out by high-speed hardware which stores only the modified data blocks Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and startedread more
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Patent
Modular computer system
TL;DR: In this paper, a multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system.
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Central processing unit with hardware controlled checkpoint and retry facilities
TL;DR: In this paper, a data processing system with a central processing unit (CPU), main store (MS), and high speed storage (HSS) interposed between the CPU and store is presented.
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Instruction retry mechanism for a data processing system
TL;DR: In this paper, an instruction retry mechanism is proposed to enable a digital data processing system having main, buffer and local stores to restart and, in most cases, recover from an error or failure in the processor hardware associated with the buffer and the local stores.
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Memory hierarchy system with journaling and copy back
Bruce A. Edson,Vincent A. Cordi +1 more
TL;DR: In this article, a hierarchical memory system has two memory units on each level, a data store and a copy back store, which contains all the changes that have been made in that data either by addition or modification.
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Common storage controller for dual processor system
Merwin H Alferness,John A Miller +1 more
TL;DR: Common storage controllers as discussed by the authors allow two or more general purpose digital computers to share a common data base by interfacing the central processors to their storage units such that when a predetermined area of the storage is being addressed by its associated processor for a write operation, a duplicate copy of the information will be written into the corresponding area associated with the other processor(s).