An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

Isolation for high density integrated circuits

The void-free pattern of isolation in a semiconductor substrate is described. There is contained within a semiconductor body a pattern of substantially vertically sided trenches. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. The depth of the pattern of trenches is greater than about 3 micrometers. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to between about 500 to 1500 nanometers from the upper surface of the trenches. A capping second insulating layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The epitaxial layer must be grown in such a way so as no spurious growth occurs upon the principal surfaces of the substrate, because such growth would prevent the satisfactory chemical-mechanical polishing of the C.V.D. insulator layer.

Method for forming a void free isolation structure utilizing etch and refill techniques

A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.

Tapered groove IC isolation

In a microelectronic device formed on a substrate 12, a pair of trenches 30, 36 branch at their intersection to provide branches 31-34 surrounding a sacrificial island 42. Sacrificial island 42 may comprise substrate material or other material or a void for absorbing the axial stresses propagated along the lengths of trenches 30, 36.

Trench isolation stress relief

A semiconductor device for element isolation comprises a semiconductor substrate having an impurity region of a first conductivity type whose impurity concentration attains the maximum at a predetermined depth from the surface in the depth direction, a trench formed to a predetermined depth in the impurity region of the first conductivity type, and an impurity diffusion region of the first conductivity type formed in the trench with an oxide film interposed and having only its bottom portion connected to the impurity region of the first conductivity type of the semiconductor substrate. In the semiconductor device, a uniform P+ high concentration region is substantially formed in a bottom portion of an isolation region, so that an isolation threshold value is not affected.

Semiconductor device for element isolation and manufacturing method thereof

This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

James Russell Houghton

Papers

Bipolar dynamic memory cell