Jan Kořenek

TL;DR: This work proposes a push-based approach to network monitoring that allows the detection, within the dataplane, of traffic aggregates, and reduces controller-dataplane communication overheads by up to two orders of magnitude with respect to state-of-the-art solutions.

TL;DR: A parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols.

TL;DR: A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA and the evolution of the largest sorting networks requires 10 hours in FPGa running at 100 MHz.

TL;DR: A unique parallel hardware architecture for hash-based exact match classification of multiple packets in each clock cycle that offers a reduction of memory replication requirements and is able to maintain a rather high throughput of matching multiple packets per clock cycle even without fully replicated memory resources in matching tables.

TL;DR: Novel method is proposed how to reduce data structure size for the family of packet classification algorithms at the cost of additional pipelined processing with only small amount of logic resources to significantly decreases overhead given by the crossproduct nature of classification rules.