http://www.eecs.ucf.edu/~dcm/Teaching/COT4810-Spring2011/Literature/SensorNetworksSurvey.pdf

Wireless sensor networks: a survey

The advancement in wireless communications and electronics has enabled the development of low-cost sensor networks. The sensor networks can be used for various application areas (e.g., health, military, home). For different application areas, there are different technical issues that researchers are currently resolving. The current state of the art of sensor networks is captured in this article, where solutions are discussed under their related protocol stack layer sections. This article also points out the open research issues and intends to spark new interests and developments in this field.

/pdf/a-survey-on-sensor-networks-5beav0ez6k.pdf

A survey on sensor networks

Wireless Communications

Alhussein Abouzeid Rensselaer Polytechnic Institute Raviraj Adve University of Toronto Dharma Agrawal University of Cincinnati Walid Ahmed Tyco M/A-COM Sonia Aissa University of Quebec, INRSEMT Huseyin Arslan University of South Florida Nallanathan Arumugam National University of Singapore Saewoong Bahk Seoul National University Claus Bauer Dolby Laboratories Brahim Bensaou Hong Kong University of Science and Technology Rick Blum Lehigh University Michael Buehrer Virginia Tech Antonio Capone Politecnico di Milano Javier Gómez Castellanos National University of Mexico Claude Castelluccia INRIA Henry Chan The Hong Kong Polytechnic University Ajit Chaturvedi Indian Institute of Technology Kanpur Jyh-Cheng Chen National Tsing Hua University Yong Huat Chew Institute for Infocomm Research Tricia Chigan Michigan Tech Dong-Ho Cho Korea Advanced Institute of Science and Tech. Jinho Choi University of New South Wales Carlos Cordeiro Philips Research USA Laurie Cuthbert Queen Mary University of London Arek Dadej University of South Australia Sajal Das University of Texas at Arlington Franco Davoli DIST University of Genoa Xiaodai Dong, University of Alberta Hassan El-sallabi Helsinki University of Technology Ozgur Ercetin Sabanci University Elza Erkip Polytechnic University Romano Fantacci University of Florence Frank Fitzek Aalborg University Mario Freire University of Beira Interior Vincent Gaudet University of Alberta Jairo Gutierrez University of Auckland Michael Hadjitheodosiou University of Maryland Zhu Han University of Maryland College Park Christian Hartmann Technische Universitat Munchen Hossam Hassanein Queen's University Soong Boon Hee Nanyang Technological University Paul Ho Simon Fraser University Antonio Iera University "Mediterranea" of Reggio Calabria Markku Juntti University of Oulu Stefan Kaiser DoCoMo Euro-Labs Nei Kato Tohoku University Dongkyun Kim Kyungpook National University Ryuji Kohno Yokohama National University Bhaskar Krishnamachari University of Southern California Giridhar Krishnamurthy Indian Institute of Technology Madras Lutz Lampe University of British Columbia Bjorn Landfeldt The University of Sydney Peter Langendoerfer IHP Microelectronics Technologies Eddie Law Ryerson University in Toronto

Wireless communications

We present VOSviewer, a freely available computer program that we have developed for constructing and viewing bibliometric maps. Unlike most computer programs that are used for bibliometric mapping, VOSviewer pays special attention to the graphical representation of bibliometric maps. The functionality of VOSviewer is especially useful for displaying large bibliometric maps in an easy-to-interpret way. The paper consists of three parts. In the first part, an overview of VOSviewer’s functionality for displaying bibliometric maps is provided. In the second part, the technical implementation of specific parts of the program is discussed. Finally, in the third part, VOSviewer’s ability to handle large maps is demonstrated by using the program to construct and display a co-citation map of 5,000 major scientific journals.

/pdf/software-survey-vosviewer-a-computer-program-for-505jc6bwmd.pdf

Software survey: VOSviewer, a computer program for bibliometric mapping.

(NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) I. THE FABRICS. 1. Introduction. A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. 2. The Manufacturing Process. The CMOS Manufacturing Process. Design Rules-The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective-Trends in Process Technology. 3. The Devices. The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. 4. The Wire. A First Glance. Interconnect Parameters-Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. II. A CIRCUIT PERSPECTIVE. 5. The CMOS Inverter. The Static CMOS Inverter-An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. 6. Designing Combinational Logic Gates in CMOS. Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. 7. Designing Sequential Logic Circuits. Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. III. A SYSTEM PERSPECTIVE. 8. Implementation Strategies for Digital ICS. From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective-The Implementation Platform of the Future. 9. Coping with Interconnect. Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. 10. Timing Issues in Digital Circuits. Timing Classification of Digital Systems. Synchronous Design-An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. 11. Designing Arithmetic Building Blocks. Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. 12. Designing Memory and Array Structures. The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. Problem Solutions. Index.

/pdf/digital-integrated-circuits-a-design-perspective-kjo4bcbri0.pdf

Digital integrated circuits: a design perspective

https://cs.gmu.edu/~jpsousa/classes/699/papers/roundy_2003.pdf

A study of low level vibrations as a power source for wireless sensor nodes

Digital integrated circuits : a design perspective

The recent interest in sensor networks has led to a number of routing schemes that use the limited resources available at sensor nodes more efficiently. These schemes typically try to find the minimum energy path to optimize energy usage at a node. In this paper we take the view that always using lowest energy paths may not be optimal from the point of view of network lifetime and long-term connectivity. To optimize these measures, we propose a new scheme called energy aware routing that uses sub-optimal paths occasionally to provide substantial gains. Simulation results are also presented that show increase in network lifetimes of up to 40% over comparable schemes like directed diffusion routing. Nodes also burn energy in a more equitable way across the network ensuring a more graceful degradation of service with time.

/pdf/energy-aware-routing-for-low-energy-ad-hoc-sensor-networks-24g02e6szo.pdf

Energy aware routing for low energy ad hoc sensor networks

Technology advances have made it conceivable to build and deploy dense wireless networks of heterogeneous nodes collecting and disseminating wide ranges of environmental data. Applications of such sensor and monitoring networks include smart homes equipped with security, identification, and personalization systems; intelligent assembly systems; warehouse inventory control; interactive learning toys; and disaster mitigation. The opportunities emerging from this technology give rise to new definitions of distributed computing and the user interface. Crucial to the success of these ubiquitous networks is the availability of small, lightweight, low-cost network elements, which the authors call PicoNodes. The authors present a configurable architecture that enables these opportunities to be efficiently realized in silicon. They believe that this energy-conscious system design and implementation methodology will lead to radio nodes that are two orders of magnitude more efficient than existing solutions.

Jan M. Rabaey

Papers

Digital integrated circuits: a design perspective

A study of low level vibrations as a power source for wireless sensor nodes

Digital integrated circuits : a design perspective

Energy aware routing for low energy ad hoc sensor networks

PicoRadio supports ad hoc ultra-low power wireless networking