J
Javier Lira
Researcher at Polytechnic University of Catalonia
Publications - 9
Citations - 85
Javier Lira is an academic researcher from Polytechnic University of Catalonia. The author has contributed to research in topics: Cache & Cache pollution. The author has an hindex of 6, co-authored 9 publications receiving 81 citations.
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Proceedings ArticleDOI
HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors
TL;DR: A novel and implementable data search algorithm for D-NUCA designs in CMP architectures, called HK-N UCA (Home Knows where to find data within the NUCA cache), which exploits migration features by providing fast and power efficient accesses to data which is located close to the requesting core.
Proceedings ArticleDOI
The auction: optimizing banks usage in Non-Uniform Cache Architectures
TL;DR: A novel mechanism based on the bank replacement policy for NUCA caches on CMP, called The Auction, which manages the cache efficiently and significantly reduces the requests to the off-chip memory by increasing the hit ratio in the NU CA cache.
Proceedings ArticleDOI
Implementing a hybrid SRAM / eDRAM NUCA architecture
TL;DR: This paper demonstrates, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are evicted, and proposes a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM.
Proceedings ArticleDOI
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors
TL;DR: A novel replacement technique is proposed that enables more intelligent replacement decisions to be taken and significantly reduces the requests to the off-chip memory by increasing the hit ratio in the NUCA cache.
Journal ArticleDOI
Replacement techniques for dynamic NUCA cache designs on CMPs
TL;DR: This paper proposes three different techniques to deal with replacements in NUCA caches, which are crucial in chip multiprocessors architectures to reduce requests to the offchip memory.