Showing papers by "Jean-Michel Portal published in 2008"

Metal filling impact on standard cells: definition of the metal fill corner concept

Abstract: The objective of this paper is to evaluate the delay impact of staggered metal filling (Metal2) on the standard cells and their associated local interconnect (Metal1). A Design Of Experiment (DOE) is used to define a large range of filling pattern shapes and positions. This set of filling patterns is then inserted in a Ring Oscillator (RO). From the filled RO simulations, the RO delay is expressed as a function of the filling pattern features. The maximal timing error between the model and the simulation is 1.3%, validating the model. The filling impact on RO delay magnifies the one introduced by the front-end process variations (PV). Consequently, the filling influence is introduced for the minimal, typical and maximal corners, defined now with Process (P), Voltage (V), Temperature (T) and Filling density (F) characteristics.

A New Embedded NVM Thin Film Cell for Low Voltage Applications

Abstract: Low voltage Non-Volatile-Memories (NVM) are a challenge for embedded applications. Logic device platforms go slowly but surely to thin silicon film technology. Based on an advanced CMOS device, SQeRAM cell demonstrates here for the first time its potential for embedded NVM applications. It operates with a 3V supply only. Both threshold voltage and mobility variations are the basis of its 300mV and more memory windows. This ∆VT is obtained with a density of 10 trapped electrons per cm. Introduction Non-Volatile-Memories architectures are facing major technological efforts [1]. Proposals to solve scaling issues are focused on gate stack shrink keeping the highest control gate coupling factor. As a consequence in a e r future, the floating gate should be abandoned to th e profit of local trapping using nanocristals [2] or trapping layer such as nitride [3]. In addition non-volatile memories are being developed to be compatible with future thin silicon film CMOS technologies: for FinFet [4] and Silicon-On-Nothing (SON) architectures [5] [6]. SQeRAM (SON based Quasinon-volatile RAM) architecture has been proposed fo r low voltage non-volatile memory cell to address embedde d NVM needs [7]. Electrical behavior of this cell is summarized in the following after a short description of process and morphology. Process and Technology SQeRAM process is described Figure 1. A doubleepitaxy of SiGe and Si is performed on a bulk subst rate. A gate stack is realized with nitride offsets, sacrif icial oxide spacers and hard mask (A). Then gate stack and thin silicon film are protected during the junction etch (B). A partial removal of SiGe creates notches, called wings, situ ated under the gate (C). Wings are filled with thin ONO stack and N+ in situ doped Polysilicon depositions (D). Then severa l anisotropic etches prepare the surfaces for the las t epitaxy (E), Source and Drain regrow keeping the wings safe (F). Figure 2 is a TEM cross-section of a resulted devic e which has been electrically characterized. As one can conclude, memory charges are stored under the channel. The original gate stack of the l ogic devices is conserved. A Thin ONO is introduced for low volt age biases. The thickness and quality of this dielectri c layer determines retention of the device. PolySilicon win gs allow to apply biases under channel without any additiona l contact. Memory principle: electrical properties SQeRAM operates a less than 3V supply. The biases used in this paper are summarized in Table 1. Read operation has been performed here with drain voltage of 0.1V. Figure 3 shows after a Write sweep a 300mV memory window wit h a maximum bias of 2.5V on the drain. Forward (FD) and Reversed (RD) Diode pulses are used to vary the sto red charge. Diode bias cycling has been used to investi gate the memory ability of the devices. Figure 4 shows the typical FD/RD cycling for the 80nm long device shown Figure 2. The ∆VT observed under threshold voltage on Figure 4a) is due to stored ch arge. A mobility variation is observed Figure 4b) for inver sion regime as already observed with traps in gate oxide by [8]. Initial mobility is not completely restored by FD p ulse. The sub-threshold slope is slightly degradated after th first RD pulse Figure 4a). As the sub-threshold slope stays quite similar during the cycle, there is no more interfac e degradation after the first pulse. States 0 and 1 are respectively defined after FD an d RD pulses. Figure 5 and 6 give memory windows after FD/RD cycle for both 30Å and 50Å gate oxide devices . In Figure 7, ∆VT memory window corresponds to the difference of gate bias applied for a same curr ent in the device at both states. Memory window is higher for thick gate oxide under threshold due to a better charge effect as gate coupling is lower. Memory window in inversion regim e is better for a 30Å oxide thickness related to mobilit y variation. Memory window study TCAD simulation is used to evaluate charge density and mobility variations for 30Å gate oxide device. Figure 8 details the simulated device. Table 2 summarizes th used parameters according TEM cross-section analysis (Fi gure 2). A constant surface charge density is assumed in the ONO in both wings. Mobility and charge density have been a dapted to fit the curve (Figure 9). Simulation considers m emory effect due to a 10 13 e/cm charge density. There is a 9.5 cm.V.s mobility variation between states 0 and 1. A 20 cm.V.s mobility degradation is observed between initial curve and state 0. Figure 10 shows the resulting memory windows from simulation versus measurements. The behavior i n inversion regime (A) is reproduced: mobility variat ion is a good way to explain ∆VT increase in this regime. In far subthreshold (B) regime it is also reproduced. The sma ll difference of sub-threshold slope between the 2 sta te (Figure 6) explains ∆VT increase during the transition (C). Conclusion More than 300mV memory window can be obtained for a density of 10 13 electrons per cm. Degradation occurs in the early steps of writing. Our study has demonstra ted that SQeRAM cell memory window depends on both threshold voltage and mobility variations. Reliability enhanc ement needs more efforts on device integration and ONO st ack. Acknowledgment: This work is supported in the frame of MINAmI Europ ean project (WP6) www.fp6-minami.org Reference [1] M. Noguchi et al., \"A High-performance Multi-l evel NAND Flash Memory with 43nm-node Floating-gate Technology\", In ter ational Electron Devices Meeting (2007) pp 445 – 448 [2] G. Molas et al., \"Thorough investigation of Sinanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flas h NAND applications\", International Electron Devices Meeting (2007) pp 45 3– 456 Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008, -830J-6-3 pp. 830-831