J
Jeffrey M. Mason
Researcher at Xilinx
Publications - 18
Citations - 704
Jeffrey M. Mason is an academic researcher from Xilinx. The author has contributed to research in topics: Cache & Reconfigurable computing. The author has an hindex of 11, co-authored 18 publications receiving 697 citations.
Papers
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Proceedings ArticleDOI
Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs
TL;DR: In this article, the authors describe architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs, augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules.
Patent
Modular design method and system for programmable logic devices
TL;DR: In this paper, a top-level logic design for a PLD is partitioned into modules and implemented independently from other modules by using a guided process, where the information generated during the partitioning of the toplevel design and the implementation of each module is used to guide the integration of the associated logic in the top level design.
Proceedings ArticleDOI
CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures
TL;DR: CHiMPS is a C-based accelerator compiler for hybrid CPU-FPGA computing platforms that inputs generic ANSIC code and automatically generates VHDL blocks for an FPGA.
Proceedings ArticleDOI
Performance and power of cache-based reconfigurable computing
Andrew Putnam,Susan J. Eggers,Dave Bennett,Eric F. Dellinger,Jeffrey M. Mason,Henry E. Styles,Prasanna Sundararajan,Ralph D. Wittig +7 more
TL;DR: The analyses and optimizations of the CHiMPS compiler that construct many-cache caches are presented, showing a performance advantage of 7.8x over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater.
Patent
Method and apparatus for providing secure intellectual property cores for a programmable logic device
Jay T. Young,Jeffrey M. Mason +1 more
TL;DR: In this article, a secure IP core for a programmable logic device (PLD) is described and a circuit design for the IP core, the circuit design is encoded to produce at least one partial configuration bitstream.