A solar cell module includes: two solar cells, each including an photoelectric conversion body 10a, 10b having first and second main faces and generating photogenerated carriers, a first electrode provided on the first main face, and a second electrode provided on the first or second main face and having a polarity opposite to that of the first electrode; and a wiring member 2a for electrically connecting the first electrode of one of the two solar cells to the second electrode of the other solar cell. The first electrode has a plurality of finger electrodes for collecting the photogenerated carriers generated in the photoelectric conversion body 10a and a bus-bar electrode 11a for collecting the photogenerated carriers collected by the plurality of finger electrodes. The wiring member 2a is connected onto the bus-bar electrode 11a of the one solar cell through a connection layer 13 formed of a conductive resin containing conductive material. The connection layer 13 is also in contact with the first main face of the photoelectric conversion body 10a.

Solar cell module

A process for making a back-contact solar cell module is provided. Electrically conductive wires of an integrated back-sheet are physically and electrically attached to the back contacts of the solar cells of a solar cell array through openings in a polymeric interlayer dielectric layer using an electrically conductive binder before thermal lamination of the module.

Integrated back-sheet for back contact photovoltaic module

A rear-contact solar cell interconnect is disclosed. The rear-contact solar cell interconnect includes a first conductive foil with an opening and a second conductive foil. The first conductive foil is arranged to be electrically connected to a first polarity contact of a solar cell. The second conductive foil is arranged to be electrically connected to a second polarity contact of the solar cell through the opening of the first conductive foil. The solar cell includes a first surface arranged to receive solar irradiation and a second surface substantially opposite the first surface. The first polarity contact and the second polarity contact are provided on the second surface of the solar cell.

Foil-based interconnect for rear-contact solar cells

An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.

System and method for stacked die embedded chip build-up

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a first part, a second part below the first part, a third part between the first and second parts, and at least one barrier layer including a metal different from a metal of the first to third parts. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Printed circuit board and method for manufacturing the same

SiC MOSFETs have demonstrated continued performance improvement and maturation in the areas of Gate oxide stability and reliability over the past years. While necessary, this alone is not sufficient to achieve reliable high voltage operation. In this paper, the design constraints impacting high voltage reliability and their impact on SiC MOSFET performance at useful operating conditions are discussed. Experimental results are demonstrated with industry benchmark, reliable operation of up to T j =200°C with 1.2kV/25mOhm SiC MOSFETs and T j =175°C, 1.7kV/450A all-SiC MOSFET Dual-Switch modules. Avalanche ruggedness of the high-performance devices is also demonstrated with single-pulse energy densities of 9–15J/cm2 recorded with Drain currents as high as ID= 90A for 0.2cm2 die.

SiC MOSFET design considerations for reliable high voltage operation

A semiconductor assembly includes a semiconductor wafer including backside contact pads coupled to respective contact regions of different signal types and insulation separating the backside contact regions by signal type. The semiconductor assembly further includes metallization situated over at least a portion of the insulation and interconnecting the backside contact pads.

Wafer level interconnection and method

A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the electronic device or to the base insulative layer; and securing the electronic device to the base insulative layer using the adhesive layer.

Method for making an interconnect structure and interconnect component recovery process

An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface, and the electronic device being secured to the base insulative layer; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer. The base insulative layer secures to the electronic device through the removable layer. The removable layer is capable of releasing the base insulative layer from the electronic device. The removal may be done without damage to a predetermined part of the electronic component.

Recoverable electronic component

Transient voltage suppressors (TVS) fabricated in silicon carbide (SiC) and subjected to extensive surge testing is presented. The SiC TVS devices can work at high temperatures, have high current density capability, are smaller and have lower capacitance than comparable Si devices. They are also rugged and reliable, capable of withstanding multiple back-to-back lightning hits. These devices are expected to provide enhanced surge protection for composite aircrafts and enable high temperature power electronics circuits.

Jeffrey Scott Erlbaum

Papers

SiC MOSFET design considerations for reliable high voltage operation

Wafer level interconnection and method

Method for making an interconnect structure and interconnect component recovery process

Recoverable electronic component

Silicon carbide transient voltage suppressor for next generation lightning protection