Negative bias temperature instability: What do we understand?

At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.

Hybrid-orientation technology (HOT): opportunities and challenges

This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

Intrinsic transistor reliability improvements from 22nm tri-gate technology

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

Device and technology evolution for Si-based RF integrated circuits

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The -direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.

Negative bias temperature instability in triple gate transistors

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

Impact of mechanical stress engineering on flicker noise characteristics

Fully working 125 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

CMOS transistors with a 70-nm gate length for 0.13-μm-node high-performance applications

The characteristics of 20 /spl Aring/ gate oxide formed by an RTO (Rapid Thermal Oxidation) process with an NO+O/sub 2/ mixture ambient have been investigated. Due to the high nitrogen concentration in the oxide, good boron penetration suppression and higher interface trap density were observed. The low thermal cycle of the RTO process facilitated the formation of SSR (Super Steep Retrograde) channel and reduced RSCE (Reverse Short Channel Effect). The transistor performance was Idsat n/p=925/370 /spl mu/A//spl mu/m for Vdd=1.5 V and Idoff n/p=10 nA//spl mu/m. The TDDB and hot carrier characteristics were evaluated and found to be satisfactory.

Jeong-Hwan Yang

Papers

Negative bias temperature instability in triple gate transistors

Impact of mechanical stress engineering on flicker noise characteristics

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

CMOS transistors with a 70-nm gate length for 0.13-μm-node high-performance applications

Device characteristics and reliability for 0.18 /spl mu/m MOSFET with 20 /spl Aring/ gate oxide formed by RTO