A method of making a lithographic printing plate comprising the steps of: a) providing a lithographic printing plate precursor comprising (i) a support having a hydrophilic surface or which is provided with a hydrophilic layer, (ii) a photopolymerizable coating on said support, b) image-wise exposing said coating in a plate setter, c) developing the precursor, thereby removing, the non-exposed areas of the coating from the support, whereby the developing step is carried out off-press in a gumming unit by treating the coating of the precursor with a gum solution.

Method of making a photopolymer printing plate

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Shadow register file for instruction rollback

A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

Semiconductor integrated circuit

The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.

Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis

In a shift register latch scan string such as that employed in level sensitive scan design (LSSD) methodologies, primary input and/or primary output signal line connections are distributed in a substantially uniform fashion along the length of the shift register scan string configuration so as to provide a mechanism for testing for fault conditions existing along the scan string.

Ordering shift register latches in a scan ring to facilitate diagnosis, testing and isolation

A three terminal circuit comprised of two semiconductor transistors of opposite polarity types and two semiconductor diodes. These semiconductors are interconnected so as to provide positive regenerative feedback in a manner which permits achieving highly stable, temperature insensitive circuit characteristics which can be made independent of circuit parameters. The circuit requires no resistors, capacitors or inductors and may be used with particular advantage in integrated circuit form. Use of the circuit as an impedance converter, current generator, voltage regulator and differential amplifier are illustrated.

Geometric current amplifier

A semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit-sense line through either one of a pair of oppositely connected bipolar transistors for reading and writing, respectively. The bit-sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit-sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for instrumenting the latching regenerative feedback amplifier.

Latch type regenerative circuit for reading a dynamic memory cell

A family of circuits characterized by storage mode operation in a switching circuit employs minority carrier injection from the base into the collector region of a semi-conductor device. The minority carrier charge stored in the collector thereafter causes amplified forward collector emitter current when forward collector potential is applied. Particular examples of the circuit family include inverters, single shot circuits, transistor oscillators and electronic switching in general.

Inverter circuits utilizing minority carrier injection in a semiconductor deivce

A family of circuits characterized by storage mode operation in a switching circuit employs minority carrier injection from the base into the collector region of a semi-conductor device. The minority carrier charge stored in the collector thereafter causes amplified forward collector emitter current when forward collector potential is applied. Particular examples of the circuit family includes inverters, single shot circuits transistor oscillators and electronic switching in general.

Jerry Saia

Papers

Ordering shift register latches in a scan ring to facilitate diagnosis, testing and isolation

Geometric current amplifier

Latch type regenerative circuit for reading a dynamic memory cell

Inverter circuits utilizing minority carrier injection in a semiconductor deivce

Timed switch circuits utilizing minority carrier injection in a semiconductor device