This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS

A wideband noise-cancelling low-noise amplifier (LNA) without the use of inductors is designed for low-voltage and low-power applications. Based on the common-gate-common-source (CG-CS) topology, a new approach employing local negative feedback is introduced between the parallel CG and CS stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the CG transistor. This leads to an LNA with higher gain and lower noise figure (NF) compared with the conventional CG-CS LNA, particularly under low power and voltage constraints. By adjusting the local open-loop gain, the NF can be optimized by distributing the power consumption among transistors and resistors based on their contribution to the NF. The optimal value of the local open-loop gain can be obtained by taking into account the effect of phase shift at high frequency. The linearity is improved by employing two types of distortion-cancelling techniques. Fabricated in a 0.13-μm RF CMOS process, the LNA achieves a voltage gain of 19 dB and an NF of 2.8-3.4 dB over a 3-dB bandwidth of 0.2-3.8 GHz. It consumes 5.7 mA from a 1-V supply and occupies an active area of only 0.025 mm2.

A Wideband Inductorless LNA With Local Feedback and Noise Cancelling for Low-Power Low-Voltage Applications

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 24-GHz band The RFSD filter test chip is fabricated in a 018-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate By changing the input sampling rate, the RFSD filter can be tuned to different RF channels A maximum input sampling rate of 1072 MS/s has been achieved A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter The RFSD filter has an IIP/sub 3/ of +55 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands The measured image rejection is 59 dB and the sampling clock jitter is 064 ps The test chip consumes 47 mW in the analog part and 40 mW in the digital part It occupies an area of 1 mm/sup 2/

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

A 1.4V wideband inductorless LNA, implemented in a 0.13mum CMOS process, consumes 25mW and occupies 0.019mm2. Measurement results show 17dB voltage gain, 7GHz BW, 2.4dB NF at 3GHz, -4.1 dBm IIP3, and -20dBm P1dB. A common-drain feedback circuit provides wideband 50Omega input matching and partial noise cancellation. A current reuse technique improves both gain and power.

A 1.4V 25mW Inductorless Wideband LNA in 0.13/spl mu/m CMOS

In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generator and response analyzer. The test is oriented at spot defects in a transceiver front-end. Estimates for noise, signal power and nonlinear distortions such as EVM (or SER), gain and IP3, respectively, are considered the test responses. Limitations of these tests are investigated with respect to the test path properties, the strength of defects and circuit tolerances. The IP3 test complements the EVM (SER) and gain tests for some spot defects. The analysis is verified by simulation of a functional-level RF transceiver model implemented in Matlab/spl trade/.

Mixed loopback BiST for RF digital transceivers

In this paper, a BiST technique for an RF transceiver front-end is presented. The test is aimed at spot defects typical of mass production in the CMOS process. The loop-back approach is used to detect faults modeled as resistive breaks or bridges. The resulting impairment in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as such are subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of a GSM transceiver with BiST is investigated to verify the proposed approach.

BiST model for IC RF-transceiver front-end

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like bit error rate, error vector magnitude, or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. This paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

/pdf/built-in-loopback-test-for-ic-rf-transceivers-j4sxv645ad.pdf

Built-in Loopback Test for IC RF Transceivers

High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (LA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of SA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

Jerzy Dabrowski

Papers

A 1.4V 25mW Inductorless Wideband LNA in 0.13/spl mu/m CMOS

Mixed loopback BiST for RF digital transceivers

BiST model for IC RF-transceiver front-end

Built-in Loopback Test for IC RF Transceivers

Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications