Inorganic semiconductor nanostructures are ideal systems for exploring a large number of novel phenomena at the nanoscale and investigating the size and dimensionality dependence of their properties for potential applications. The use of such nanostructures with tailored geometries as building blocks is also expected to play crucial roles in future nanodevices. Since the discovery of carbon nanotubes much attention has been paid to exploring the usage of inorganic semiconductor nanostructures as field-emitters due to their low work functions, high aspect ratios and mechanical stabilities, and high electrical and thermal conductivities. This article provides a comprehensive review of the state-of-the-art research activities in the field. It mainly focuses on the most widely studied inorganic nanostructures, such as ZnO, ZnS, Si, WO3, AlN, SiC, and their field-emission properties. We begin with a survey of inorganic semiconductor nanostructures and the field-emission principle, and then discuss the recent progresses on several kinds of important nanostructures and their field-emission characteristics in detail and overview some additional inorganic semiconducting nanomaterials in short. Finally, we conclude this review with some perspectives and outlook on the future developments in this area.

Inorganic semiconductor nanostructures and their field-emission applications

Semiconductor Power Devices

The need for high power density and high temperature capabilities in today's electronic devices continues to grow. More robust devices with reliable and stable functioning capabilities are needed, for example in aerospace and automotive industries as well as sensor technology. These devices need to perform under extreme temperature conditions, and not show any deterioration in terms of switching speeds, junction temperatures, and power density, and so on. While the bulk of research is performed to source and manufacture these high temperature devices, the device interconnect technology remains under high focus for packaging. The die attach material has to withstand high temperatures generated during device functioning and also cope with external conditions which will directly determine how well the device performs in the field. This literature work seeks to review the numerous research attempts thus far for high temperature die attach materials on wide band gap materials of silicon carbide, gallium nitride and diamond, document their successes, concerns and application possibilities, all of which are essential for high temperature reliability.

Die Attach Materials for High Temperature Applications: A Review

Mechanical properties of nano-silver joints as die attach materials

Recently, high-temperature power devices have become a popular discussion topic because of their various potential applications in the automotive, down-hole oil and gas industries for well logging, aircraft, space exploration, nuclear environments, and radars. Devices for these applications are fabricated on silicon carbide-based semiconductor material. For these devices to perform effectively, an appropriate die attach material with specific requirements must be selected and employed correctly. This article presents a review of this topic, with a focus on the die attach materials operating at temperatures higher than 623 K (350 °C). Future challenges and prospects related to high-temperature die attach materials also are proposed at the end of this article.

A Review on Die Attach Materials for SiC-Based High-Temperature Power Devices

A nanoscale silver paste containing 30-nm silver particles that can be sintered at 280degC was made for interconnecting semiconductor devices. Sintering of the paste produced a microstructure containing micrometer-size porosity and a relative density of around 80%. Electrical and thermal conductivities of around 2.6times105 (Omegamiddotcm)-1 and 2.4W/K-cm, respectively, were obtained, which are much higher than those of the solder alloys that are currently used for die attachment and/or flip-chip interconnection of power semiconductor devices. The sintered porous silver had an apparent elastic modulus of about 9GPa, which is substantially lower than that of bulk silver, as well as most solder materials. The lower elastic modulus of the porous silver may be beneficial in achieving a more reliable joint between the device and substrate because of increased compliance that can better accommodate stress arising from thermal expansion mismatch

Low-Temperature Sintered Nanoscale Silver as a Novel Semiconductor Device-Metallized Substrate Interconnect Material

A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125°C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275°C with the sintered joints having the melting temperature of silver at 961°C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications.

Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area $({>}100~{\rm mm}^{2})$ Chips

Screen/stencil-printable nanosilver pastes were processed and characterized for die-attaching SiC devices. The nanosilver pastes were made by mixing silver particles in diameter with an organic binder vehicle. For the die-attachment, the nanosilver pastes were printed onto silver-coated or gold-coated direct-bond-copper (DBC) substrates. After die-attaching the SiC devices, the assemblies were heated to 300 with a 40-min dwell time to develop bonding up to 40 MPa on the silver-coated substrates, which was comparable to that of the Pb37Sn63 solder die-attachment. Scanning acoustic microscopy (SAM) of the sintered silver die-attachment did not reveal any detectable voids, while scanning electron microscopy (SEM) showed the presence of uniformly distributed microscale pores. Because of the porous microstructure of the sintered silver and its low apparent elastic modulus, it could help relieve thermomechanical stresses in the die-attachment assembly. Finally, since silver die-attachment is almost pure in constituent (>99%), the die-attachment could enable packaging of wide bandgap semiconductors devices, such as SiC or GaN, for high-temperature operation.

Processing and Characterization of Nanosilver Pastes for Die-Attaching SiC Devices

A paste including metal or metal alloy particles (which are preferably silver or silver alloy), a dispersant material, and a binder is used to form an electrical, mechanical or thermal interconnect between a device and a substrate. By using nanoscale particles (i.e., those which are less than 500 nm in size and most preferably less than 100 nm in size), the metal or metal alloy particles can be sintered at a low temperature to form a metal or metal alloy layer which is desired to allow good electrical, thermal and mechanical bonding, yet the metal or metal alloy layer can enable usage at a high temperature such as would be desired for SiC, GaN, or diamond (e.g., wide bandgap devices). Furthermore, significant application of pressure to form the densified layers is not required, as would be the case with micrometer sized particles. In addition, the binder can be varied so as to insulate the metal particles until a desired sintering temperature is reached; thereby permitting fast and complete sintering to be achieved.

Nanoscale metal paste for interconnect and method of use

Control of the low-temperature sintering of nanosilver particles was attained by dispersing and stabilizing nanosilver particles into a paste form using the selected organic binder systems. As demonstrated by scanning electron microscopy (SEM) and thermogravimetric analysis (TGA), with the existing binder systems, undesirable premature coalescence of nanosilver particles was prevented and the metastable structure was retained until the binder burned out at relatively higher temperatures. Enhanced densification was achieved upon the binder burnout because at the relatively higher temperatures the densification mechanisms, e.g., grain-boundary or lattice diffusion, become more dominant. We propose that the onset of sintering, extent of densification, and final grain size can be controlled by either the size of the initial nanosilver particles or the binder systems with different burnout characteristics.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0884291400027060

Jesus N. Calata

Papers

Low-Temperature Sintered Nanoscale Silver as a Novel Semiconductor Device-Metallized Substrate Interconnect Material

Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area $({>}100~{\rm mm}^{2})$ Chips

Processing and Characterization of Nanosilver Pastes for Die-Attaching SiC Devices

Nanoscale metal paste for interconnect and method of use

Control of nanosilver sintering attained through organic binder burnout