An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate. The first fin has a first gate region and the second fin has a second gate region. The method also includes forming a metal-gate line over the first and second gate regions. The metal-gate line extends from the first fin to the second fin. The method also includes applying a line-cut to separate the metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming an isolation region within the line cut.

Method of cutting metal gate

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation; a fin structure of the crystalline semiconductor material overlying the substrate; a gate structure over a portion of the fin structure; an epitaxy layer over another portion of the fin structure, the epitaxy layer having a surface having a second crystal plane orientation, wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the surface of the epitaxy layer and the top surface of the substrate.

Method of fabricating a FinFET device

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Fin-like field effect transistor (finfet) device and method of manufacturing same

A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

Finfet devices with unique fin shape and the fabrication thereof

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.

Layout for multiple-fin sram cell

A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region.

Cell structure for dual port sram

An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.

Cell layout for SRAM FinFET transistors

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second pass-gate devices configured with the two cross-coupled inverters to form a port for data access, wherein the first and second pull-down devices each includes a first channel doping feature of a first doping concentration, and the first and second pass-gate devices each includes a second channel doping feature of a second doping concentration greater than the first doping concentration.

Structure and method for SRAM cell circuit

The present invention discloses an interconnect structure for an integrated circuit formed on a semiconductor substrate In one embodiment, the first conductive layer is formed above the semiconductor substrate A first via contact is formed on the first conductive layer A second via contact is formed on the first via contact A second conductive layer is formed on the second via contact One of the first and second via contacts has a cross-sectional area substantially larger that of another for improving a landing margin thereof, thereby eliminating a need of using a landing pad between the first and second via contacts

Jhon Jhy Liaw

Papers

Layout for multiple-fin sram cell

Cell structure for dual port sram

Cell layout for SRAM FinFET transistors

Structure and method for SRAM cell circuit

Interconnect structure for integrated circuits