A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series and a corresponding set of multiple gate stages connected in series, where the output stages have the same structure as the corresponding gate stages. The switches that the provide the output of each output generation stage are controlled by the corresponding gate stage. The number of output stages that are active in boosting the voltage self-adapts according to the output level being regulated, with the later stages changing from a boosting operation to a filtering function with not being used to active boost the output.

Self-Adaptive Multi-Stage Charge Pump

Techniques of operating a charge pump are described. The charge pump is connectable to receive a clock signal and a regulating voltage and provide an output voltage. The charge pump can have one or multiple stages, each of the stages will include a capacitor. During the charging phase, the regulating voltage is used to regulate the potential of the capacitor's bottom plate. During the boosting phase, the capacitor's top plate is connected to supply the output for the stage and the bottom plate is connected to receive the stage's input. Each stage will also have a set of switching elements, allowing the capacitor to be alternately connected in the charging and boosting phases. For the first stage, the input is derived from the clock signal, and for any subsequent stages, the input will be the output of the preceding stage. The last stage provides the output voltage of the pump.

Bottom plate regulation of charge pumps

A charge pump system using a current based regulation method, in addition to the typical voltage based regulation methods is presented. The current flow in the charge pump is determined independently of the output voltage. By sensing the current going through the charge pump while its output is being regulated to the target level, the strength of charge pump can be dynamically adjusted in term of regulation level, branch assignment, clock frequency, clock amplitude, and so on. Indirectly sensing the current going through pump (not in serial with output stage to allow additional IR drop) will allow the pumps to have matrix of V and I to better adjust the charge pump parameters for current saving and ripple reduction.

Charge pump with current based regulation

A charge pump system for supplying an output voltage to a load is described. The charge pump system includes a charge pump connected to receive an input voltage generate from it the output voltage. The system also includes regulation circuitry connected to receive the output voltage and a reference voltage, where the regulation circuitry is connected to the charge pump to regulate the output voltage based upon the values of the reference voltage and the output voltage. During ramp up or a recovery operation the output voltage is initially regulated according to a first level and subsequently regulated to a second level higher than the first level, the second level corresponding to a desired regulated output voltage.

Techniques to Reduce Charge Pump Overshoot

A charge pump system is formed on an integrated circuit that can be connected to an external power supply. The system includes a charge pump and a clock generator circuit. The clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates an output voltage from an input voltage. The clock frequency is a decreasing function of the voltage level of the external power supply. This allows for reducing power consumption in the charge pump system formed on a circuit connectable to an external power supply.

Clock Generator Circuit for a Charge Pump

A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Digital circuit to measure and/or correct duty cycles

A hybrid phase locked loop (PLL) circuit for obtaining stabilized dynamic response and independent adjustment of damping factor and loop bandwidth is provided. The hybrid PLL circuit of the illustrative embodiments includes the resistance/capacitance (RC) filter elements of a conventional RC PLL and the feed-forward path from the output of the phase frequency detector to the voltage controlled oscillator (VCO). The hybrid PLL essentially enhances the performance of the conventional feed-forward PLL by providing the RC filter whose components can be weighted to provide a dynamic response that is significantly less sensitive to parameter variation and which allows loop bandwidth optimization without sacrificing damping.

Jieming Qi

Papers

Digital circuit to measure and/or correct duty cycles

Phase Locked Loop with Stabilized Dynamic Response