Multilevel inverter (MLI) topologies play a crucial role in the dc–ac power conversion due to their high-quality performance and efficiency. This article aims to propose a new switched-capacitor-based boost multilevel inverter topology (SCMLI). The proposed topology consists of nine power semiconductor switches with one dc voltage source and two capacitors, capable of generating a nine-level output voltage waveform with twice voltage gain. With the addition of two switches, the proposed topology can be used for higher voltage-gain applications. Other features of the proposed topology include the self-voltage balancing of the capacitors, parallel operation of the capacitors, lower voltage stress across the switches, along with the inherent polarity changing capability. To obtain the high-quality output waveform, a selective harmonic elimination pulsewidth modulation technique is applied. In this technique, the detrimental low-order harmonics can easily be regulated and eliminated from the output voltage of MLI. The proposed topology is compared with the recently introduced SCMLI topologies considering various parameters to set the benchmark of the proposed topology. The performance of the proposed MLI is investigated through various experimental results using a laboratory prototype setup.

Single-Phase Step-Up Switched-Capacitor-Based Multilevel Inverter Topology With SHEPWM

An efficient and cost-effective power converter is a pre-requisite for the modern power applications. With the evolvement of matured medium power self-commutated switching devices, multilevel inverters (MLIs) are emerged as a promising solution for high-power medium-voltage applications. Though, MLIs are performing a promising role in industrial applications, their high device count, size, cost and control complexities have restricted their market penetration. To address the disadvantages of MLIs, researchers are continuously contributing to new generation topologies under the name of reduced switch count (RSC) MLIs. From the past decade, numerous RSC-MLIs topologies have been reported for various applications. Therefore, this paper presents a comprehensive review and classification of RSC-MLI topologies, in terms of their structure, features, limitations, suitability and selection for specific applications.

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A Survey on Reduced Switch Count Multilevel Inverters

The superior power quality of the multilevel inverter (MLI) compared to the two-level counterpart has increased its suitability for medium and high power applications. In the present work, a switched capacitor MLI topology has been presented, which utilises lesser switches and dc power supply and generates a 13-level output voltage. The detailed analysis along with simulation and hardware results have been presented. The comparative performance of the proposed topology has also been presented.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2019.1567

Dual asymmetrical dc voltage source based switched capacitor boost multilevel inverter topology

A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2019.0826

Dual input switched-capacitor-based single-phase hybrid boost multilevel inverter topology with reduced number of components

Switched-capacitor-based multilevel inverters for boost-type dc–ac power conversions usually exhibit a trade-off between the switch count and switch-voltage rating, i.e., a reduction of one necessitating an increase of the other. Such a dilemma is well addressed in this article by proposing a novel single-phase nine-level inverter based on a switched-capacitor network with a single switch. The proposed inverter then reduces the number of switches while generating a boosted dc-link voltage. A unique six-switch full-bridge cooperating with a low-frequency half-bridge further steps-up the output voltage with a quadruple gain. The voltage stresses on the power devices are, however, maintained low even under the boosted high output voltage, as all the switches/diodes can be clamped to any of the low-voltage capacitors. Consequently, low-voltage power devices can be utilized, reducing the overall power loss. Detailed theoretical analysis, calculations, and design considerations of the proposed inverter are provided. Comparisons with the prior-art inverters illustrate its advantages. Simulations and experimental tests on a 1-kVA inverter prototype verify the above-claimed benefits. 

/pdf/a-single-source-nine-level-boost-inverter-with-a-low-switch-1vec95z5.pdf

A Single-Source Nine-Level Boost Inverter With a Low Switch Count

The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies.

Jing Fang Wong

Papers

Improved Switched-Capacitor Integrated Multilevel Inverter With a DC Source String