Traditional timing analysis employs a delay model that assumes only a single input switches for a gate during a transition, while all side inputs are held constant to noncontrolling values. However, ignoring the impact of multiple-input switching (MIS) can lead to either an overestimation or an underestimation of a gate delay. In this article, we examine the impact of MIS in the delay of different types of gates under varying conditions of load, slew, and temporal distance of signals at the inputs. We model the impact of MIS by deriving a corrective measure that should be applied to the conventional single-input switching (SIS) delay under different conditions. We call this corrective measure as MIS-SIS difference (MSD). In this work, we have evaluated polynomial regressions, support vector regression, and artificial neural networks (ANNs) to model MSD. Additionally, we integrate the ANN-based MSD model into existing timing libraries and employ them in carrying out MIS-aware timing analysis. We test the proposed methodology on some benchmark circuits and demonstrate that the proposed technique can improve the accuracy of timing analysis effectively. For example, for ISCAS’85 C17 circuit having short paths, under the MIS scenario, traditional SIS-based delay differs from the corresponding SPICE-computed delay by as large as 120%. However, the delay computed using the proposed methodology under the MIS scenario for the same circuit differs from the SPICE-computed delay by less than 3%. Additionally, the runtime overhead of the proposed methodology during timing analysis is negligible.

Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning

Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper proposes architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact of variations on the delay of circuit paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated for advanced technology nodes, where transistor dimensions reach atomic levels and established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily, process-variation/aging-aware static timing analysis (STA) equips designers with accurate statistical delay distributions. Timing guardbands that are small, yet sufficient, can then be effectively estimated. However, such analysis is costly as it requires intensive Monte-Carlo simulations. Further, it necessitates access to confidential physics-based aging models to generate the standard-cell libraries required for STA. In this work, we employ graph neural networks (GNNs) to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit. Our proposed GNN4REL framework empowers designers to perform rapid and accurate reliability estimations without accessing transistor models, standard-cell libraries, or even STA; these components are all incorporated into the GNN model via training by the foundry. Specifically, GNN4REL is trained on a FinFET technology model that is calibrated against industrial 14-nm measurement data. Through our extensive experiments on EPFL and ITC-99 benchmarks, as well as RISC-V processors, we successfully estimate delay degradations of all paths—notably within seconds—with a mean absolute error down to 0.01 percentage points.

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Sub/near-threshold static random-access memory (SRAM) design is crucial for addressing the memory bottleneck in power-constrained applications. However, the high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a “rare event” in memory circuits, the time and storage overhead of conventional simulations based on the Monte Carlo (MC) analysis cannot be tolerated. On the other hand, classic analytical methods predicting failure probabilities from a physical expression become inaccurate in the sub/near-threshold voltage domain due to the hypothetical distribution or the oversimplified drain current (<inline-formula> <tex-math notation="LaTeX">$I_{ds}$ </tex-math></inline-formula>) model for nanoscale devices. This work first proposes a simple but efficient empirical <inline-formula> <tex-math notation="LaTeX">$I_{ds}$ </tex-math></inline-formula> model to describe the drain-induced barrier lowering (DIBL) effect. Based on that, the probability density functions of the interest metrics in SRAM are derived. Two analytical models are then put forward to evaluate SRAM dynamic stabilities, including the access time failure and the write failure. The proposed models can be extended easily to different types of SRAM with different read/write-assist circuits. The models are validated against MC simulations across different operating voltages and temperatures. The average relative errors at 0.5-V <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ DD}}$ </tex-math></inline-formula> are only 8.8% for the access-time failure model and 10.4% for the write failure model. The size of the required sample data set is <inline-formula> <tex-math notation="LaTeX">$43.6\times $ </tex-math></inline-formula> smaller than that of the state-of-the-art method.

A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model

In the advanced technology nodes, process parameter variations are increasingly resulting in unpredictable device behavior. The issue is even aggravated by low power requirements which stretches the transistor operation into near-threshold regime. Despite device simulation gives precise results, it is time-consuming for static timing analysis and dynamic timing analysis. In this paper, we propose VASTA, a statistical timing analysis tool based on the variation-aware standard cell library. The tool efficiently supports statistical static timing analysis (SSTA) and statistical dynamic timing analysis (SDTA). The standard cell library models delay under operating environment effects by using quadratic regressions and multivariate adaptive regression splines. VASTA works on industry formats (. $v$ and. $sdc$ ) and is designed to run in parallel during both SSTA and SDTA. The statistical cell library is built and verified using SMIC 40 nm and 28 nm PDK. The mean and standard deviation errors of cell delay models are 2.77% and 1.68% compared with SPICE simulation results under 10k Monte Carlo samples. The SSTA and SDTA are tested with ISCAS85, ISCAS89, and EPFL benchmark suites. The average mean and standard deviation errors of SSTA are 4.01% and 2.03%, which are similar to SDTA. Meanwhile, our SDTA is 17.7 times faster than traditional corner-based dynamic timing analysis which relies on generating. $vcd$ cell activity files.

/pdf/vasta-a-wide-voltage-statistical-timing-analysis-tool-based-1a3npvv8lv.pdf

VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models

Voltage scaling technique is widely employed in state-of-the-art low power circuits with excellent power reduction. However, voltage scaling to sub-threshold (STV) and near-threshold (NTV) domain introduces performance degradation and high process variation sensitivity. Accurate modeling of the statistical characteristics especially the probability distribution function (PDF) and the cumulative distribution function (CDF) is urgently required with process variation consideration. In this paper, a novel analytical model is derived based on log-skew-normal (LSN) distribution to precisely evaluate the gate delay variation. The multi-variate threshold variation in stacked gates are modeled with a linear approximation method in delay distribution derivation. By applying the CDF of the proposed model, the maximum and minimum delay indicated by ±3σ percentile point can be calculated essentially different from the common method with much higher accuracy. Experimental results show the proposed model is highly fitted with Monte Carlo (MC) results for stochastic delay modeling of generic logic gates in near/subthreshold regime with less than 8% and 6% error in delay variability and ±3σ delay prediction, showing maximum accuracy improvement about 40 times compared to preproposal models.

/pdf/an-analytical-gate-delay-model-in-near-subthreshold-domain-3iwupque80.pdf

An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation

The increasing performance variation poses remarkable challenges to timing analysis for circuits operating in near-threshold voltage (NTV) region in spite of attractive energy efficiency advantage. Few researches were devoted to the statistical timing model for NTV design especially when input transition time was considered. In this paper, a statistical timing model for CMOS inverter is proposed in NTV region under process variation considering fast and slow input, which is derived analytically with a novel segmented step approximation method to overcome the integral issue of drain current equation for ramp input. The mean and variance of inverter delay distribution are derived as a function of the supply voltage, inverter size, load capacitance, and input transition time with the statistical characteristics of process variation. Experimental results under 40nm process show that the proposed inverter delay model is highly fitted with Monte Carlo (MC) simulation results at the supply voltage of 0.4V, where the mean and variance error are less than 5.35% and 8.36% for fast input and 10.89% and 13.07% for slow input respectively.

A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time

Path delay variation becomes a serious concern in advanced technology, especially for multi-corner conditions. Plenty of timing analysis methods have been proposed to solve the issue of path delay variation, but they mainly focus on every single corner and are based on a characterized timing library, which neglects the correlation among multiple corners, resulting in a high characterization effort for all required corners. Here, a novel prediction framework is proposed for path delay variation by employing a learning-based method using back propagation (BP) regression. It can be used to solve the issue of path delay variation prediction under a single corner. Moreover, for multi-corner conditions, the proposed framework can be further expanded to predict corners that are not included in the training set. Experimental results show that the proposed model outperforms the traditional Advanced On-Chip Variation (AOCV) method with 1.4X improvement for the prediction of path delay variation for single corners. Additionally, while predicting new corners, the maximum error is 4.59%, which is less than current state-of-the-art works.

https://www.mdpi.com/2079-9292/9/1/157/pdf

Novel Prediction Framework for Path Delay Variation Based on Learning Method

The increasing performance variation and non-Gaussian distribution pose remarkable challenges to timing analysis for circuits operating in low voltage region. Accurate modeling of the statistical characteristics is urgently required with process variation consideration. In this paper, the statistical models for drain current and gate delay in low voltage region are established in analytical form based on the log-skew-normal (LSN) distribution via moment matching technique. Experimental results show that the probability distribution function (PDF) curves obtained from the proposed models for drain current and gate delay are highly fitted with Monte Carlo (MC) simulation results in sub/near-threshold regions. Moreover, owing to the proposed LSN-based statistical model, less than 8% error is introduced in the predicted sensitivity of gate delay and the maximum/minimum delay indicated by ±3σ percentile points can be calculated more precisely than the LN-based method with up to 3× accuracy improvement for low supply voltage.

Jingjing Guo

Papers

An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation

A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time

Novel Prediction Framework for Path Delay Variation Based on Learning Method

A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region

An efficient path delay variability model for wide-voltage-range digital circuits