J
Jinquan Dai
Researcher at Intel
Publications - 29
Citations - 1208
Jinquan Dai is an academic researcher from Intel. The author has contributed to research in topics: Scalability & Critical section. The author has an hindex of 13, co-authored 29 publications receiving 1128 citations.
Papers
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Proceedings ArticleDOI
The HiBench benchmark suite: Characterization of the MapReduce-based data analysis
TL;DR: This paper presents the benchmarking, evaluation and characterization of Hadoop, an open-source implementation of MapReduce, and introduces HiBench, a new benchmark suite for Hadoops, which evaluates and characterize theHadoop framework in terms of speed, throughput, and system resource utilizations.
Proceedings ArticleDOI
HiTune: dataflow-based performance analysis for big data cloud
TL;DR: HiTune as mentioned in this paper is a performance analyzer for Hadoop based on distributed instrumentations and dataflow-driven performance analysis, which can help users to efficiently conduct performance analysis and tuning, demonstrating the benefits of dataflowbased analysis and the limitations of existing approaches.
Proceedings ArticleDOI
Towards high-quality I/O virtualization
TL;DR: This work has developed new techniques for high-quality I/O virtualization (including device semantic preservation, essential principles for avoiding device virtualization holes, and real-time VMM scheduler extensions), using directI/O with hardware IOMMU, which not only meets the requirements of high quality I/o virtualization, but also is the basis for PCI-SIG I/ O Virtualization (IOV).
Journal ArticleDOI
Automatically partitioning packet processing applications for pipelined architectures
TL;DR: A novel program transformation technique to exploit parallel and pipelined computing power of modern network processors is presented and results show that the method provides impressive speed up for the commonly used NPF IPv4 forwarding and IP forwarding benchmarks.
Patent
Automatic caching generation in network applications
TL;DR: Automatic software controlled caching generations in network applications are described in this paper, where one or more directives and/or instructions are inserted into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor.