From the Publisher: 
The accessible presentation of this book gives both a general view of the entire computer vision enterprise and also offers sufficient detail to be able to build useful applications. Users learn techniques that have proven to be useful by first-hand experience and a wide range of mathematical methods. A CD-ROM with every copy of the text contains source code for programming practice, color images, and illustrative movies. Comprehensive and up-to-date, this book includes essential topics that either reflect practical significance or are of theoretical importance. Topics are discussed in substantial and increasing depth. Application surveys describe numerous important application areas such as image based rendering and digital libraries. Many important algorithms broken down and illustrated in pseudo code. Appropriate for use by engineers as a comprehensive reference to the computer vision enterprise.

Computer vision : a modern approach = 计算机视觉 : 一种现代的方法

Machine-Learning tasks are becoming pervasive in a broad range of domains, and in a broad range of systems (from embedded systems to data centers). At the same time, a small set of machine-learning algorithms (especially Convolutional and Deep Neural Networks, i.e., CNNs and DNNs) are proving to be state-of-the-art across many applications. As architectures evolve towards heterogeneous multi-cores composed of a mix of cores and accelerators, a machine-learning accelerator can achieve the rare combination of efficiency (due to the small number of target algorithms) and broad application scope. Until now, most machine-learning accelerator designs have focused on efficiently implementing the computational part of the algorithms. However, recent state-of-the-art CNNs and DNNs are characterized by their large size. In this study, we design an accelerator for large-scale CNNs and DNNs, with a special emphasis on the impact of memory on accelerator design, performance and energy. We show that it is possible to design an accelerator with a high throughput, capable of performing 452 GOP/s (key NN operations such as synaptic weight multiplications and neurons outputs additions) in a small footprint of 3.02 mm2 and 485 mW; compared to a 128-bit 2GHz SIMD processor, the accelerator is 117.87x faster, and it can reduce the total energy by 21.08x. The accelerator characteristics are obtained after layout at 65 nm. Such a high throughput in a small footprint can open up the usage of state-of-the-art machine-learning algorithms in a broad set of systems and for a broad set of applications.

https://novel.ict.ac.cn/ychen/pdf/DianNao.pdf

DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory

Large deep neural network models have recently demonstrated state-of-the-art accuracy on hard visual recognition tasks. Unfortunately such models are extremely time consuming to train and require large amount of compute cycles. We describe the design and implementation of a distributed system called Adam comprised of commodity server machines to train such models that exhibits world-class performance, scaling and task accuracy on visual recognition tasks. Adam achieves high efficiency and scalability through whole system co-design that optimizes and balances workload computation and communication. We exploit asynchrony throughout the system to improve performance and show that it additionally improves the accuracy of trained models. Adam is significantly more efficient and scalable than was previously thought possible and used 30x fewer machines to train a large 2 billion connection model to 2x higher accuracy in comparable time on the ImageNet 22,000 category image classification task than the system that previously held the record for this benchmark. We also show that task accuracy improves with larger models. Our results provide compelling evidence that a distributed systems-driven approach to deep learning using current training algorithms is worth pursuing.

/pdf/project-adam-building-an-efficient-and-scalable-deep-mz26kixwji.pdf

Project Adam: building an efficient and scalable deep learning training system

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

Increasing database size and massive dimensions of keypoint descriptors caused nearest neighbor searching as a main bottleneck in object recognition systems. Therefore a high throughput approximate nearest neighbor (ANN) searching processor is proposed for real-time object recognition. To reduce the external bandwidth required in nearest neighbor searching, this chip utilizes an on-chip cache for transaction reduction and the zeroless locality-sensitive hashing (zeroless-LSH) operation for required data suppression. As a result, the proposed ANN-searching processor achieves 62,720 vectors/sec throughput and 1,140GOPS/W power efficiency, which are 1.45x and 1.37x higher than the state-of-the-art respectively, enabling real-time object recognition for Full-HD 30fps video streams.

/pdf/a-86mw-98gops-ann-searching-processor-for-full-hd-30fps-3v8w68orm3.pdf

A 86mW 98GOPS ANN-searching processor for Full-HD 30fps video object recognition with zeroless locality-sensitive hashing

Heterogeneous multi-core object recognition processor with Reinforcement Learning (RL) NoC is proposed for efficient portable HD object recognition. RL NoC automatically learns management policies in the network of heterogeneous system without an explicit modeling. By adopting RL NoC, the throughput performances of feature detection and description are increased by 20.4% and 11.5%, respectively. As a result, the overall execution time of the object recognition is reduced by 38%. The implemented chip achieves 121mW power consumption with 1.24 TOPS/W power efficiency.

/pdf/online-reinforcement-learning-noc-for-portable-hd-object-3uajdspz8n.pdf

Online Reinforcement Learning NoC for portable HD object recognition processor

This paper presents an area and power efficient cellular neural network (CNN) that enables real-time image processing. The proposed shared synapse architecture halves the number of required synapse multipliers, which are the main contributor to area and power consumption of CNNs. For this, a current holder circuit is used to sample and hold the currents of non-changing synaptic circuit outputs. Compared to the conventional architecture of CNNs, power and area are reduced by 46% and 41%, respectively.

/pdf/an-area-efficient-shared-synapse-cellular-neural-network-for-1t8d76uphi.pdf

An area efficient shared synapse cellular neural network for low power image processing

A mixed-mode neuro-fuzzy accelerator is proposed for keypoint localization of image features of Scale Invariant Feature Transform (SIFT) algorithm. To reduce processing time of keypoint localization with low power consumption, analog Adaptive Neuro-Fuzzy Inference System (ANFIS) and digital controller are implemented together. It is implemented in 0.13µm CMOS process and achieves 1.15mW power consumption. Compared to the conventional digital standalone system, 0.733mm2 neuro-fuzzy accelerator achieves 43% processing time reduction and also results in 19.4% time reduction of image feature extraction process.

/pdf/1-15mw-mixed-mode-neuro-fuzzy-accelerator-for-keypoint-1qhbf46wba.pdf

1.15mW mixed-mode neuro-fuzzy accelerator for keypoint localization in image processing

This paper presents an asynchronous digital-analog mixed-mode neuro-fuzzy controller that enables energy efficient implementation of machine intelligence SoC. The proposed neuro-fuzzy controller adopts an asynchronous 2-stage pipeline for analog and digital domain operations, which is the main contributor to high throughput and energy efficient machine intelligence SoC. To this end, a neuro-fuzzy controller with a delay prediction unit and a new ISA is introduced to modify the stage depth of mixed-mode pipeline incorporating with highly parallel special function units. Compared to the conventional digital standalone VLSI architecture, power reduction and processing speed acceleration are achieved by 46.6% and 71.4%, respectively, reporting 12.5μJ/epoch energy efficiency.

/pdf/an-asynchronous-mixed-mode-neuro-fuzzy-controller-for-energy-5eoo3f32vr.pdf

Jinwook Oh

Papers

A 86mW 98GOPS ANN-searching processor for Full-HD 30fps video object recognition with zeroless locality-sensitive hashing

Online Reinforcement Learning NoC for portable HD object recognition processor

An area efficient shared synapse cellular neural network for low power image processing

1.15mW mixed-mode neuro-fuzzy accelerator for keypoint localization in image processing

An asynchronous mixed-mode neuro-fuzzy controller for energy efficient machine intelligence SoC