Jinwook Oh

TL;DR: An intelligent inference engine (IIE) is proposed as a hardware controller for a many-core processor to satisfy the requirements of low-power real-time object recognition.

TL;DR: A new low-power object-recognition processor achieves real-time robust recognition, satisfying modern mobile vision systems' requirements, and an attention-based object- recognition algorithm for energy efficiency, a heterogeneous multicore architecture for data- and thread-level parallelism, and a network on a chip for high on-chip bandwidth.

TL;DR: In this paper, an apparatus and method for supporting simultaneous multiple iterations (SMI) in a course-grained reconfigurable architecture (CGRA) is presented, which includes hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight, and a control unit including hardware structures to maintain synchronization and initiate and terminate loops within the PEs.

TL;DR: A neuro-fuzzy controller performs intelligent ROI estimation by mimicking the human visual system, then manages the processor's overall pipeline stages using workload-aware task scheduling and applied database size control.

TL;DR: A high throughput ANN-searching processor is proposed for high-resolution (full-HD) and real-time (30 fps) video object recognition and adopts an interframe cache architecture as a hardware-oriented approach and a zeroless locality-sensitive-hashing (zeroless-LSH) algorithm as a software- oriented approach to reduce the external memory bandwidth required in nearest neighbor searching.