The use of silicon nanostructures in solar cells offers a number of benefits, such as the fact they can be used on flexible substrates. A silicon wire-array structure, containing reflecting nanoparticles for enhanced absorption, is now shown to achieve 96% peak absorption efficiency, capturing 85% of light with only 1% of the silicon used in comparable commercial cells. Si wire arrays are a promising architecture for solar-energy-harvesting applications, and may offer a mechanically flexible alternative to Si wafers for photovoltaics1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17. To achieve competitive conversion efficiencies, the wires must absorb sunlight over a broad range of wavelengths and incidence angles, despite occupying only a modest fraction of the array’s volume. Here, we show that arrays having less than 5% areal fraction of wires can achieve up to 96% peak absorption, and that they can absorb up to 85% of day-integrated, above-bandgap direct sunlight. In fact, these arrays show enhanced near-infrared absorption, which allows their overall sunlight absorption to exceed the ray-optics light-trapping absorption limit18 for an equivalent volume of randomly textured planar Si, over a broad range of incidence angles. We furthermore demonstrate that the light absorbed by Si wire arrays can be collected with a peak external quantum efficiency of 0.89, and that they show broadband, near-unity internal quantum efficiency for carrier collection through a radial semiconductor/liquid junction at the surface of each wire. The observed absorption enhancement and collection efficiency enable a cell geometry that not only uses 1/100th the material of traditional wafer-based devices, but also may offer increased photovoltaic efficiency owing to an effective optical concentration of up to 20 times.

Enhanced absorption and carrier collection in Si wire arrays for photovoltaic applications

Semiconductor nanowires represent an important class of nanostructure building block for photovoltaics as well as direct solar-to-fuel application because of their high surface area, tunable bandgap and efficient charge transport and collection. In this talk, I will highlight several recent examples in this lab using semiconductor nanowires and their heterostructures for the purpose of solar energy harvesting. In addition, we have also discovered that the thermoconductivity of the silicon nanowires can be significantly reduced due to phonon scattering, pointing to a very promising approach to design better thermoelectrical materials. It is important to note that the engines that generate most of the world's power typically operate at only 30–40 per cent efficiency, releasing roughly 15 terawatts of heat to the environment. If this “wasted heat” could be recycled, the impact globally would be enormous. Our silicon nanowire thermoelectric technology could have a significant impact in alternative energy generation.

Semiconductor nanowires for energy conversion.

Solar energy represents one of the most abundant and yet least harvested sources of renewable energy. In recent years, tremendous progress has been made in developing photovoltaics that can be potentially mass deployed. Of particular interest to cost-effective solar cells is to use novel device structures and materials processing for enabling acceptable efficiencies. In this regard, here, we report the direct growth of highly regular, single-crystalline nanopillar arrays of optically active semiconductors on aluminium substrates that are then configured as solar-cell modules. As an example, we demonstrate a photovoltaic structure that incorporates three-dimensional, single-crystalline n-CdS nanopillars, embedded in polycrystalline thin films of p-CdTe, to enable high absorption of light and efficient collection of the carriers. Through experiments and modelling, we demonstrate the potency of this approach for enabling highly versatile solar modules on both rigid and flexible substrates with enhanced carrier collection efficiency arising from the geometric configuration of the nanopillars.

http://nano.eecs.berkeley.edu/publications/NatureMat_2009_SNOPcell.pdf

Three-dimensional nanopillar-array photovoltaics on low-cost and flexible substrates

Silicon nanowire-based solar cells on metal foil are described. The key benefits of such devices are discussed, followed by optical reflectance, current-voltage, and external quantum efficiency data for a cell design employing a thin amorphous silicon layer deposited on the nanowire array to form the p-n junction. A promising current density of ∼1.6mA∕cm2 for 1.8cm2 cells was obtained, and a broad external quantum efficiency was measured with a maximum value of ∼12% at 690nm. The optical reflectance of the silicon nanowire solar cells is reduced by one to two orders of magnitude compared to planar cells.

Silicon nanowire solar cells

We have demonstrated a low-temperature wafer-scale etching and thin film deposition method for fabricating silicon n−p core−shell nanowire solar cells. Our devices showed efficiencies up to nearly 0.5%, limited primarily by interfacial recombination and high series resistance. Surface passivation and contact optimization will be critical to improve device performance in the future.

/pdf/silicon-nanowire-radial-p-n-junction-solar-cells-vub1m1o03t.pdf

Silicon nanowire radial p-n junction solar cells.

The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.

Comparison of 4H-SiC MOSFETs on (0001), (000-1) and (11-20) Oriented Substrates

In this work, solar-blind UV 4H-SiC avalanche photodetectors were fabricated and tested in linear and Geiger modes. APDs with both PIN and separate absorption and multiplication (SAM) structures were investigated. PIN structures demonstrated higher quantum efficiencies while the SAM structure exhibit lower leakage currents. Deposition of a thin film optical filter on top of the devices was used to provide a high photon rejection ratio of (Stas add value here). However, an external filter showed a better photon rejection ratio compared to the deposited one by about one order of magnitude.

Solar-Blind 4H-SiC Avalanche Photodiodes

There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.

Dimension profiling of SiC devices

In this article, we describe the coating of silicon nanowire arrays with thin dielectric layers using Plasma Enhanced Chemical Vapor Deposition (PECVD). The impact of deposition pressure, temperature, and nanowire array density on the silicon oxide coating thickness uniformity was assessed using a detailed electron microscopy observations of the nanowire arrays. Deposition rates were found to vary along the nanowire length as a function of the above process parameters, and ranged from 0 to 35 nm/min. The coating thickness was found to be most uniform at higher pressures and temperatures, and high-density nanowire arrays with smaller nanowire diameters and larger lengths led to the deposition of coating with a smaller thickness gradient along the wire length.

Conformal dielectric films on silicon nanowire arrays by plasma enhanced chemical vapor deposition

We explain the role of nitrogen in simultaneously increasing the inversion channel mobility and reducing the threshold voltage of SiC MOSFET. A variety of computational techniques have been used to compute the atomic scale configuration of a nitridated SiC/SiO2 interface, and the corresponding change in Fermi level, inversion channel mobility, and threshold voltage. X-ray photoelectron spectroscopy (XPS) has been used to investigate the SiC/SiO2 interface to determine the nitrogen concentrations and chemical bonding. We elucidate the physics behind improved channel mobility due to NO anneal and demonstrate that the trade-off between threshold voltage and inversion channel mobility can be correlated to the extent of nitridation.

Jody Fronheiser

Papers

Comparison of 4H-SiC MOSFETs on (0001), (000-1) and (11-20) Oriented Substrates

Solar-Blind 4H-SiC Avalanche Photodiodes

Dimension profiling of SiC devices

Conformal dielectric films on silicon nanowire arrays by plasma enhanced chemical vapor deposition

Multiscale Modeling and Analysis of the Nitridation Effect of SiC/SiO2 Interface